基于AlteraFPGA的DpramIPcore设计
时间:2019-12-20
大小:27.06MB
阅读数:152
查看他发布的资源
资料介绍
包含整个工程和modelsim仿真文件。读写地址及读写使能是通过数据产生模块来产生。dpramcore\datagenerate.v.bak.........\.b\altsyncram_13s1.tdf.........\..\altsyncram_3gi1.tdf.........\..\altsyncram_lqr1.tdf.........\..\dpram_core.amm.cdb.........\..\dpram_core.asm.qmsg.........\..\dpram_core.asm.rdb.........\..\dpram_core.asm_labs.ddb.........\..\dpram_core.cbx.xml.........\..\dpram_core.cmp.bpm.........\..\dpram_core.cmp.cdb.........\..\dpram_core.cmp.hdb.........\..\dpram_core.cmp.kpt.........\..\dpram_core.cmp.logdb.........\..\dpram_core.cmp.rdb.........\..\dpram_core.cmp2.ddb.........\..\dpram_core.cmp_merge.kpt.........\..\dpram_core.db_info.........\..\dpram_core.eda.qmsg.........\..\dpram_core.fit.qmsg.........\..\dpram_core.hier_info.........\..\dpram_core.hif.........\..\dpram_core.idb.cdb.........\..\dpram_core.lpc.html.........\..\dpram_core.lpc.rdb.........\..\dpram_core.lpc.txt.........\..\dpram_core.map.bpm.........\..\dpram_core.map.cdb.........\..\dpram_core.map.hdb.........\..\dpram_core.map.kpt.........\..\dpram_core.map.logdb.........\..\dpram_core.map.qmsg.........\..\dpram_core.map_bb.cdb.........\..\dpram_core.map_bb.hdb.........\..\dpram_core.map_bb.logdb.........\..\dpram_core.pre_map.cdb.........\..\dpram_core.pre_map.hdb.........\..\dpram_core.rpp.qmsg.........\..\dpram_core.rtlv.hdb.........\..\dpram_core.rtlv_sg.cdb.........\..\dpram_core.rtlv_sg_swap.cdb.........\..\dpram_core.sgate.rvd.........\..\dpram_core.sgate_sm.rvd.........\..\dpram_core.sgdiff.cdb.........\..\dpram_core.sgdiff.hdb.........\..\dpram_core.sld_design_entry.sci.........\..\dpram_core.sld_design_entry_dsc.sci.........\..\dpram_core.smart_action.txt.........\..\dpram_core.sta.qmsg.........\..\dpram_core.sta.rdb.........\..\dpram_core.sta_cmp.6_slow_1200mv_85c.tdb.........\..\dpram_core.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd.........\..\dpram_core.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd.........\..\dpram_core.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd.........\..\dpram_core.syn_hier_info.........\..\dpram_core.tiscmp.fast_1200mv_0c.ddb.........\..\dpram_core.tiscmp.slow_1200mv_0c.ddb.........\..\dpram_core.tiscmp.slow_1200mv_85c.ddb.........\..\dpram_core.tis_db_list.ddb.........\..\dpram_core.tmw_info.........\..\logic_util_heursitic.dat.........\..\prev_cmp_dpram_core.qmsg.........\dpram.bsf.........\dpram.qip.........\dpram.v.........\dpram_bb.v.........\dpram_core.asm.rpt.........\dpram_core.done.........\dpram_core.eda.rpt.........\dpram_core.fit.rpt.........\dpram_core.fit.smsg.........\dpram_core.fit.summary.........\dpram_core.flow.rpt.........\dpram_core.map.rpt.........\dpram_core.map.summary.........\dpram_core.pin.........\dpram_core.pof.........\dpram_core.qpf.........\dpram_core.qsf.........\dpram_core.sof.........\dpram_core.sta.rpt.........\dpram_core.sta.summary.........\dpram_core.v.........\dpram_core.v.bak.........\dpram_core_nativelink_simulation.rpt.........\dpram_inst.v.........\dpram_syn.v.........\greybox_tmp\cbx_args.txt.........\incremental_db\compiled_partitions\dpram_core.db_info.........\..............\...................\dpram_core.root_partition.cmp.cbp.........\..............\...................\dpram_core.root_partition.cmp.cdb.........\..............\...................\dpram_core.root_partition.cmp.dfp.........\..............\...................\dpram_core.root_partition.cmp.hdb.........\..............\...................\dpram_core.root_partition.cmp.kpt.........\..............\...................\dpram_core.root_partition.cmp.logdb.........\..............\...................\dpram_core.root_partition.cmp.rcfdb.........\..............\...................\dpram_core.root_partition.cmp.re.rcfdb.........\..............\...................\dpram_core.root_partition.map.cbp.........\..............\...................\dpram_core.root_partition.map.cdb.........\..............\...................\dpram_core.root_partition.map.dpi……
版权说明:本资料由用户提供并上传,仅用于学习交流;若内容存在侵权,请进行举报,或
联系我们 删除。