硬件电子琴/*-------------------------------------------------------- -- Engineer: zhrscut -- Create Date: -- Module Name: -- Tool Versions: Quartus_II 9.1 -- 欢迎加入 EEPW ，FPGA 开发板 DIY 活动 --------------------------------------------------------*/ module piano(clk,key,beep,led); input clk; input[7:0] key; output beep; output[7:0] led; reg beep; reg[7:0] led; reg[15:0] cnt,freq; always @(posedge clk) begin if(cnt cnt=cnt+1; else begin cnt=0; beep=~beep; end end always @(key) begin case(key) 8'b1111_1110:begin freq //1 8'b1111_1101:begin freq //2 ……