动态数码管显示/*-------------------------------------------------------- -- Engineer: zhrscut -- Create Date: -- Module Name: -- Tool Versions: Quartus_II 9.1 -- 欢迎加入 EEPW ，FPGA 开发板 DIY 活动 --------------------------------------------------------*/ module dyn_segled(clk,data,sel); input clk; output[7:0] data; output[7:0] sel; reg[7:0] data; reg[7:0] sel; reg[22:0] cnt; reg[2:0] dyn_led; always @(posedge clk) begin cnt dyn_led end //------------------------------------------------------------------------------- /* ;0, 1, 2, 3, 4, 5, 6, 7, db c0h,f9h,a4h,b0h,99h,92h,82h,f8h */ Parameter seg0 = 7'hc0, we0=8'b1111_1110, seg1 = 7'hf9, we1=8'b1111_1101, ……