【应用手册】AN 578: Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT Devices This application note describes the steps involved in the manual placement of CMU phase-locked loops (PLLs) and ATX PLLs in Altera’s Stratix® IV GX and GT FPGAs. Altera’s Quartus® II software automatically places the CMU PLLs and ATX PLLs by default. The default placement of CMU PLLs by the Quartus II software may not be optimum for all bonded configurations, except for the PCI Express (PIPE) ×8 bonded configuration and the Basic ×8 bonded configuration. Check the default placement to decide if it is optimum for skew requirements in your Basic (PMA Direct) ×N bonded design. If it is not, manual placement of the CMU PLLs is recommended. The default placement of ATX PLLs by the Quartus II software is performed arbitrarily for all bonded configurations, except for the PCI Express (PIPE) ×8 bonded configuration. Check the default placement to decide if it is optimum for skew requirements in your design. If it is not, manual placement of the ATX PLLs is recommended. This application note uses the Basic (PMA Direct) xN bonded configuration as an example scenario, where skew is a critical parameter and is dependent on the location of the transmitter PLL (CMU PLL or ATX PLL). AN 578: Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT Devices May 2009 AN-578-1.0 Introduction This application note describes the steps involved in the manual placement of CMU phase-locked loops (PLLs) and ATX PLLs in Altera’s Stratix IV GX and GT FPGAs. Altera’s Quartus II software automatically places the CMU PLLs and ATX PLLs by default. The default placement……