In an R-2R DAC design with supply voltages exceeding ±5V, large voltage glitches (up to 1.5V) can occur during the DAC's major-carry transitions. These glitches can propagate through the output buffer amplifier and appear at output. The slewing of the level shifters that control the top (VREF+) and bottom (VREF-) single-pole double-throw switches (S0 to SN) causes the glitchesMaxim > App Notes > A/D and D/A CONVERSION/SAMPLING CIRCUITS Keywords: Deglitching Techniques for High-Voltage R-2R DACs May 01, 2001 APPLICATION NOTE 583 Deglitching Techniques for High-Voltage R-2R DACs In an R-2R DAC design with supply voltages exceeding ±5V, large voltage glitches (up to 1.5V) can occur during the DAC's major-carry transitions. These glitches can propagate through the output buffer amplifier and appear at output. The slewing of the level shifters that control the top (VREF+) and bottom (VREF-) single-pole double- throw switches (S0 to SN) causes the glitches (Figure 1). If each switch of the "inverted" R-2R ladder were turned on and/or off instantaneously, glitch amplitudes at the DAC output (or input of the output buffer ampli……