原创
VHDL写的RTL级利用LCELL实现的延时环（记录）
- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- ENTITY forced_delay IS
- GENERIC (N : INTEGER := 20); --number of forced delay buffers
- PORT (
- din : IN STD_LOGIC;
- dout : OUT STD_LOGIC);
- END forced_delay;
- ARCHITECTURE arch OF forced_delay IS
- SIGNAL a:STD_LOGIC_VECTOR (N downto 1);
- COMPONENT LCELL
- PORT (
- a_in : IN STD_LOGIC;
- a_out : OUT STD_LOGIC);
- END COMPONENT;
- BEGIN
- LC_1: LCELL PORT MAP(a_in=>din,a_out=>a(1));
- Gen_delay : FOR i in 1 to N-1 GENERATE
- LC : LCELL PORT MAP(a_in=>a(i),a_out=>a(i+1));
- END GENERATE;
- dout<=a(N);
- END arch;
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- ENTITY pd IS
- PORT
- (
- pulse :in std_logic;
- pulse_d :out std_logic
- );
- end pd;
- architecture beha of pd is
- -- N gives the pulse delay multiplier. pulse_delay = N*lcell_delay
- -- N must be adjusted to be coherent to pulse_delay desired and lcell_delay of using device
- -- logic cell delay can be found in device performance documentation
- constant N : integer := 17;
- -- lcell array with N elements
- signal delay_line: std_logic_vector(N-1 downto 0);
- -- these attributes force synthesizer to keep our buffer alone
- -- this ensures that delay is the expected
- attribute keep: boolean;
- attribute keep of delay_line: signal is true;
- begin
- gen_delay:
- for i IN 1 TO N-1 generate
- delay_line(i) <= delay_line(i-1);
- end generate;
- delay_line(0) <= pulse;
- pulse_d <= delay_line(N-1);
- end beha;
关闭
站长推荐
/1 
第三代功率半导体器件测试解决方案 直播时间： 03月06日 10:00
文章评论（0条评论）
登录后参与讨论