原创 Synopsys Design Compiler-A quick Tutorial(copied)

copy from: http://www.vlsiip.com/dc_shell/

Design Compiler user guide
Step 0. Invoke Design Compiler

           
unix> dc_shell-t



Step 1. Setup technology library. To synthesize a design you need
technology library which will contain

       description of the cells from the
fab, and their timing. This is usually a .db file found in

       library installation directory. To
do this

     1(a). Tell synopsys where your
<library>.db file is.

           set search_path
{/homes/amittal/s5/work/physical_lib/corelib/tsmc_090_g_art}

     1(b). Tell synopsys what is your technology
library, which you want to map your design on called

           set target_library
{scadv_tsmc_cln90g_lvt_ss_0p9v_125c.db}

     1(c). Set up link libraries. This is optional
.db files which are pre synthesized and ready to be read in

     For this, append your search path where your
optional .db files are

           lappend search_path
{[exec pwd]}

          
lappend search_path {.}

     1(d). Set up link libraries. This is optional
.db files which are pre synthesized and ready to be read in

           set
link_library  {PLL10CCMID_W_125_1.35.db}

Step 2. Read In your design files

     2(a). if it is verilog:

           read_verilog
counter.v

     2(b). if it is vhdl: As it is in this tutorial

           read_vhdl
counter.vhd

           read_vhdl
counter_top.vhd

     2(c). if it is ddc:

           read_ddc counter.ddc

Step 3. Set Design Constraints:

     3(a) Set frequency of operation: You have to
create a clock in the design,

     With a given timeperiod. The command below
creates a clock and calls it

     'design_clk' with a timeperiod of 10 ns,
(100MHz), and maps it to the

      'clk' input of the design.

           create_clock
-period 10 -name design_clk clk

     3(b) Set input constraints : Set how much time
would be spent by

     signals arriving into your design, outside
your design with respect to the clock

           set_input_delay 4.0
[remove_from_collection [all_inputs ] clk] -clock design_clk

     3(c) Set output constraints : Set how much
time would be spent by

     signals leaving your desing, outside your
design, before they are captured by

     the same clock

           set_output_delay
7.0 [all_outputs] -clock design_clk

     3(d) Set area constraints : set maximum
allowed area to 0 . well its just to

     instruct design compiler that use as less area
as possible.

           set_max_area 0

Step 4. Enable clock gating for low power (optional)

     4(a) The following commands will try to insert
clock gates for each 2 registers

           set_clock_gating_style
-minimum_bitwidth 2

Step 5. Write formal verification setupfile (optional)

           set_svf -append
"counter.svf"

Step 6. Set Register optimization veriables (optional)

     (a) Set automatic removal of constant
flipflop(s)

           set
compile_seqmap_propagate_constants true

     (b) Set automatic removal of unloaded
flipflop(s)

          
set compile_delete_unloaded_sequential_cells false

Step 7. Set mapping of sync resets to aviod Xs in sims (optional)

           set
hdlin_ff_always_sync_set_reset "true"

Step 8. Set the name of top level as current design and compile the
design

     (a)  current_design
counter_top

           compile -map_effort
high

     (b) If you are using dc ultra :

           compile_ultra

           You
may want to turn off output inversion of sequential cells

           compile_ultra
-no_seq_output_inversion

Step 9. Write design output netlist

     9(a).Write output in ddc format

           write -format ddc
-output counter.ddc -hier

     9(b).Write output in verilog format 

           write -format ddc
-output counter.vlog -hier

Step 10. You may want to flatten your design before writing out netlist

           ungroup -all
-flatten

           write -format
verilog -output counter_flat.vlog

Step 11. Writing a timing report of your design

           report_timing >
counter_timing.rep

Step 12. Quit Design Compiler

           quit

    





More random
DC shell Tcl
mode Commands:



define_design_lib lib1 -path ~/misc/vhdl

analyze -library lib1 -format vhdl /homes/amittal/misc/vhdl/xx.vhdl

get_design_lib_path SYNTH

get_design_lib_path work



read_verilog mse.v







report_timing -delay max -from
ARRAYCACHE_I/CACHEDIRRAM_I/regfile64x704_assembly_0/RA_ram[3] -to
pCacheMemReqFifoDataOut



report_timing -delay max -through  [find net
ARRAYCACHE_I/CACHEDIRRAM_I/regfile64x704_assembly_0/RA_ram[3]]



report_constraint -verbose -all_violators



create_clock -name "myclk" -period 13 [get_ports pClk]



set_output_delay 1.0 -clock [get_clocks myclk] 
pCacheMemReqFifoDataOut[161]



set_wire_load_mode segmented



set_wire_load_mode enclosed



update_timing



report_timing -from [find pin ARRAYCACHE_I/LatencyReqReg*/Q] -to
pCacheMemReqFifoDataOut



report_timing -from [find pin ARRAYCACHE_I/CACHE_DATA_RAM/DO*] -to
pCacheMemReqFifoDataOut



set_output_delay 1.0 -clock myclk pCacheMemReqFifoDataOut



set_false_path -through [find pin ARRAYCACHE_I/FracSetReg*/*]index



It is to be noted that if there are no constraints, 'set_false_path'
does not actually works.



I tried to find delays to a output port, without any constraints, form
a known point in the design.

I got that.

Then I wanted to find next worst path to that output port, to I set a
false path on the path found above.

But it wouldn't work

I then created a clcok and constrainted the output port,

!! False path worked.... magic



create_clock -period 4.8 -name vclk

set_input_delay 2.5 pDmaReadRegIndex -clock vclk -add_delay

set_output_delay 2.5 pInsertNopOut -clock vclk -add_delay

set_false_path -from vclk -to PESWITCH_pClk

set_false_path -from PESWITCH_pClk -to vclk

set_false_path -from PESWITCH_pClk -through pDmaReadRegIndex -to
pInsertNopOut

report_timing -from pDmaReadRegIndex -to pInsertNopOut



set_input_delay [expr 0.35*$vclk_period] [all_inputs] -clock vclk
-add_delay

set_output_delay [expr 0.35*$vclk_period] [all_outputs] -clock vclk
-add_delay

set_false_path -from PESWITCH_pClk -through [all_inputs] -to
[all_outputs]





set compile_log_format "%elap_time %area %wns %tns %drc %endpoint
%group_path"