原创 北京流歌科技专注于嵌入式与FPGA结合的复杂系统的研究设计

DSP、MCU、FPGA/CPL 目前电子控制IC阵营的3个主流器件，各有各的优势。复杂外设的控制系统都要求CPU相对有高的接口扩展性，或者超高的运转频率，但这无疑在软硬件方面的设计复杂度上对设计者提出了更多的要求。如何利用各种中低端IC的组合设计出可以并行运转的软件执行效率相对较高的操作平台，

这样做的好处有如下三点：

(1) 提升产品性价比

      高端器件的设计成本、采购成本、生产成本都是低端器件的N倍，多U平台在大幅度的提升产品性能的同时，也大幅度的降低了产品的成本；

(2)规避设计风险 .

      高端器件有些技术的门槛是目前技术公司难以跨越的，比如高频、EMC、高速高密度PCB设计、并行软件系统的设计复杂度等。多U平台可以利用各种IC的特定优势避开这些风险大的设计技术，加速项目设计周期的稳固性。所谓平民化的技术也就是这个意思。

(3)最适合设计团队的验证理念

      有了这些相对独立完整，可以局部验证的技术，无疑也加强了功能验证方面的验证手段，这也是现在大型项目的最消耗资源的地方。所以多U平台的方案更适合用来对多个设计领域的团队相互协作巩固了验证基础。

     基于以上的几点主要优势，专门 组建QQ群 140387495，来讨论这一平民化技术在具体的实施中的设计实现细节。

第一篇：利用STM32的FSMC与FPGA/CPLD组建

    stm32的IC结构图

     先说说stm32的FSMC的技术，根据官方提供的参考代码，FSMC的介绍如下

     The STM32F10xxx flexible static memory controller (FSMC) is an embedded external
memory controller that allows the STM32F10xxx microcontroller to interface with a wide
range of memories, including SRAM, NOR Flash, NAND Flash and LCD modules.

To control a NOR Flash/SRAM memory, the FSMC provides the following features:
● Select the bank to be used to map the NOR Flash/SRAM memory: there are four
independent banks that can be used to interface with NOR Flash/SRAM/PSRAM
memories, and each bank is selected using a separate Chip Select pin.
● Enable or disable the address/data multiplexing feature
● Select the memory type to be used: NOR Flash/SRAM/PSRAM
● Define the external memory databus width: 8/16 bits
● Enable or disable the burst access mode for NOR Flash synchronous memories
● Configure the use of the wait signal: enable/disable, polarity setting and timing
configuration
● Enable or disable the extended mode: this mode is used to access the memory with
different timing configurations for read and write operations.

参考应用代码如下

void TFT_FSMCConfig(void)
{
  FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
  FSMC_NORSRAMTimingInitTypeDef  p;

  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
 
  p.FSMC_AddressSetupTime = 0x02;
  p.FSMC_AddressHoldTime = 0x00;
  p.FSMC_DataSetupTime = 0x05;
  p.FSMC_BusTurnAroundDuration = 0x00;
  p.FSMC_CLKDivision = 0x00;
  p.FSMC_DataLatency = 0x00;
  p.FSMC_AccessMode = FSMC_AccessMode_B;

  FSMC_NORSRAMInitStructure.FSMC_Bank                 = FSMC_Bank1_NORSRAM1;
  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux       = FSMC_DataAddressMux_Disable;
  FSMC_NORSRAMInitStructure.FSMC_MemoryType           = FSMC_MemoryType_NOR;
  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth      = FSMC_MemoryDataWidth_16b;
  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode      = FSMC_BurstAccessMode_Disable;
  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity   = FSMC_WaitSignalPolarity_Low;
  FSMC_NORSRAMInitStructure.FSMC_WrapMode             = FSMC_WrapMode_Disable;
  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive     = FSMC_WaitSignalActive_BeforeWaitState;
  FSMC_NORSRAMInitStructure.FSMC_WriteOperation       = FSMC_WriteOperation_Enable;
  FSMC_NORSRAMInitStructure.FSMC_WaitSignal           = FSMC_WaitSignal_Disable;
  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode         = FSMC_ExtendedMode_Disable;
  FSMC_NORSRAMInitStructure.FSMC_WriteBurst           = FSMC_WriteBurst_Disable;
  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct    = &p;  

  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
  /* Enable FSMC Bank1_SRAM Bank */
  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
  }
 

void TFT_Init(void)
{
    TFT_CtrlLinesConfig();
    TFT_FSMCConfig();
 
 TFT_RST0;
 DelayLCD(100000);
 TFT_RST1;
 DelayLCD(100000);
#if defined TFT_DRIVER_ILI9320
    TFT_Send_REG(0x00E5, 0x8000);     // Set the internal vcore voltage                                 
    TFT_Send_REG(0x0000, 0x0001);     // Start internal OSC.
    TFT_Send_REG(0x0001, 0x0100);    // set SS and SM bit
    TFT_Send_REG(0x0002, 0x0700);    // set 1 line inversion
    TFT_Send_REG(0x0003, 0x1030);     // set GRAM write direction and BGR=1. 
    TFT_Send_REG(0x0004, 0x0000);    // Resize register
    TFT_Send_REG(0x0008, 0x0202);     // set the back porch and front porch
    TFT_Send_REG(0x0009, 0x0000);     // set non-display area refresh cycle ISC[3:0]
    TFT_Send_REG(0x000A, 0x0000);    // FMARK function
    TFT_Send_REG(0x000C, 0x0000);         // RGB interface setting
    TFT_Send_REG(0x000D, 0x0000);    // Frame marker Position
    TFT_Send_REG(0x000F, 0x0000);         // RGB interface polarity
  
  //*************Power On sequence ****************//
    TFT_Send_REG(0x0010, 0x0000);          // SAP, BT[3:0], AP, DSTB, SLP, STB
    TFT_Send_REG(0x0011, 0x0007);         // DC1[2:0], DC0[2:0], VC[2:0]
    TFT_Send_REG(0x0012, 0x0000);         // VREG1OUT voltage
    TFT_Send_REG(0x0013, 0x0000);          // VDV[4:0] for VCOM amplitude
      DelayLCD(200);                                // Dis-charge capacitor power voltage
    TFT_Send_REG(0x0010, 0x17B0);          // SAP, BT[3:0], AP, DSTB, SLP, STB
    TFT_Send_REG(0x0011, 0x0147);         // DC1[2:0], DC0[2:0], VC[2:0]
      DelayLCD(50);              // Delay 50ms  
    TFT_Send_REG(0x0012, 0x013C);         // VREG1OUT voltage
      DelayLCD(50);              // Delay 50ms
    TFT_Send_REG(0x0013, 0x0E00);          // VDV[4:0] for VCOM amplitude
    TFT_Send_REG(0x0029, 0x0009);         // VCM[4:0] for VCOMH
      DelayLCD(50);    
    TFT_Send_REG(0x0020, 0x0000);          // GRAM horizontal Address
    TFT_Send_REG(0x0021, 0x0000);          // GRAM Vertical Address
  
  // ----------- Adjust the Gamma  Curve ----------//
    TFT_Send_REG(0x0030, 0x0207);  
    TFT_Send_REG(0x0031, 0x0505);  
    TFT_Send_REG(0x0032, 0x0102);
    TFT_Send_REG(0x0035, 0x0006);  
    TFT_Send_REG(0x0036, 0x0606);  
    TFT_Send_REG(0x0037, 0x0707);  
    TFT_Send_REG(0x0038, 0x0506);  
    TFT_Send_REG(0x0039, 0x0407);
    TFT_Send_REG(0x003C, 0x0106);  
    TFT_Send_REG(0x003D, 0x0601); 
  //------------------ Set GRAM area ---------------//
    TFT_Send_REG(0x0050, 0x0000);     // Horizontal GRAM Start Address
    TFT_Send_REG(0x0051, 0x00EF);     // Horizontal GRAM End Address
    TFT_Send_REG(0x0052, 0x0000);     // Vertical GRAM Start Address
 TFT_Send_REG(0x0053, 0x013F);     // Vertical GRAM Start Address
      
    TFT_Send_REG(0x0060, 0x2700);     // Gate Scan Line
    TFT_Send_REG(0x0061, 0x0001);     // NDL,VLE, REV
    TFT_Send_REG(0x006A, 0x0000);     // set scrolling line
  
  //-------------- Partial Display Control ---------//
    TFT_Send_REG(0x0080, 0x0000);
    TFT_Send_REG(0x0081, 0x0000);
    TFT_Send_REG(0x0082, 0x0000);
    TFT_Send_REG(0x0083, 0x0000);
    TFT_Send_REG(0x0084, 0x0000);
    TFT_Send_REG(0x0085, 0x0000);
    
  //-------------- Panel Control -------------------//
    TFT_Send_REG(0x0090, 0x0010);
    TFT_Send_REG(0x0092, 0x0000);
    TFT_Send_REG(0x0093, 0x0003);
    TFT_Send_REG(0x0095, 0x0110);
    TFT_Send_REG(0x0097, 0x0000);
    TFT_Send_REG(0x0098, 0x0000);

    TFT_Send_REG(0x0007, 0x0173);     // 262K color and display ON

#elif defined TFT_DRIVER_ILI9325

    TFT_Send_REG(0X0015 ,0X0030);
 TFT_Send_REG(0X009A ,0X0010);
 TFT_Send_REG(0X0011 ,0X0020);
 TFT_Send_REG(0X0010 ,0X3428);
 TFT_Send_REG(0X0012 ,0X0004);
 TFT_Send_REG(0X0013 ,0X1050);

 DelayLCD(1000);

 TFT_Send_REG(0X0012 ,0X0014);

    DelayLCD(1000);

 TFT_Send_REG(0X0010 ,0X3420);
 TFT_Send_REG(0X0013 ,0X3050);

 DelayLCD(1000);

 TFT_Send_REG(0X0030 ,0X0003);

 TFT_Send_REG(0X0031 ,0X0305);
 TFT_Send_REG(0X0032 ,0X0004);
 TFT_Send_REG(0X0033 ,0X0304);
 TFT_Send_REG(0X0034 ,0X0004);
 TFT_Send_REG(0X0035 ,0X0303);
 TFT_Send_REG(0X0036 ,0X0606);
 TFT_Send_REG(0X0037 ,0X0403);
 TFT_Send_REG(0X0038 ,0X050f);
 TFT_Send_REG(0X0039 ,0X0510);

    DelayLCD(1000);

 TFT_Send_REG(0X0001 ,0X0100);
 TFT_Send_REG(0X0002 ,0X0300);
 TFT_Send_REG(0X0003 ,0X1030);
 
 TFT_Send_REG(0X0008 ,0X0808);
 TFT_Send_REG(0X000A ,0X0008);

    DelayLCD(1000);

    TFT_Send_REG(0x0020 ,0x0000);//XÖ¸Õë
    TFT_Send_REG(0x0021 ,0x0000);//YÖ¸Õë
    TFT_Send_REG(0x0050 ,0x0000);//´°¿ÚXÖáÆðʼ×ø±ê
    TFT_Send_REG(0x0051 ,0x00EF);//´°¿ÚXÖáÖÕµã×ø±ê
    TFT_Send_REG(0x0052 ,0x0000);//´°¿ÚYÖáÆðʼ×ø±ê
    TFT_Send_REG(0x0053 ,0x013F);//´°¿ÚYÖáÖÕµã×ø±ê  
 TFT_Send_REG(0X0060 ,0X2700)

 TFT_Send_REG(0X0061 ,0X0003);//NDL|VLE|REV <2:0>
 TFT_Send_REG(0X0090 ,0X013E);//½Ó¿Ú¿ØÖÆ
 TFT_Send_REG(0X0092 ,0X010F);//½Ó¿Ú¿ØÖÆ
 TFT_Send_REG(0X0093 ,0X0001);//½Ó¿Ú¿ØÖÆ
 TFT_Send_REG(0X00A0 ,0X3000);
 TFT_Send_REG(0X00A3 ,0X0010);

    DelayLCD(1000);

 TFT_Send_REG(0X0007 ,0X0001);//0X0007ÊÇÒ»¸öÉýѹ¿ØÖƵļĴæÆ÷£¬Òª¾­¹ý²»Í¬µÄÊýÖµ°ÑµçѹÉýÉÏÈ¥
 TFT_Send_REG(0X0007 ,0X0021);
 TFT_Send_REG(0X0007 ,0X0023);
 TFT_Send_REG(0X0007 ,0X0033);
 TFT_Send_REG(0X0007 ,0X0133);
#endif

 
 DelayLCD(100000);
    Clear_TFT();

}

下面我们来设计一块应用fsmc与FPGA/cpld的单板、具体化这一设计的思路

板卡需求：

1.stm32的ucGUI/freeRtos系统

  RTC、UcGUI/FreeRtos、usb-Device/Uart1-3路、Can一路、FLASH、SDCARD、zigbee

2.基于ALtera的Cyclone IV 的FPGA的1000M以太网控制系统，相关外调如下：

  DDR2、FLASH、USB、4路高速AD1255、2路高速DA9833

 两者通过FSMC相联，原理框图如下

sm32部分因为官方推出的各种应用方案随处即是、具体看后面的原理图设计

下面我们分阶段来介绍这一简单多U系统的设计实现、