原创 verilog三分频

面试的时候 面试管叫又D触发器搭三分频电路，想了半天，没有弄出来，现在自己写了一下。
module div(clk,reset,divclk);
input  clk;
input  reset;
output      divclk;
reg        divclk1;
reg        divclk2;       
reg[1:0]   counter1;
reg[1:0]   counter2;
always@(posedge clk)
begin
 if(!reset)
　　counter1<=2'b00;
 else if(counter1==2'b10)

      counter1 <=2'b00;
 
 else
 
     counter1<=counter1+2'b01;

 if(counter1==2'b0)

    divclk1<=~divclk1;

 else if(counter1==2'b10)

    divclk1<=~divclk1;
 
end

always@(negedge clk)
begin
 if(!reset)
 
   counter2<=2'b00;

 else if(counter2==2'b10)
 
   counter2<=2'b00;
 
else
 
   counter2<=counter2+2'b01;
 
 if(counter2==2'b00)
  
       divclk2<=~divclk2;

 else if(counter2==2'b10)
   
    divclk2<=~divclk2;

end



assign divclk=divclk1|divclk2;
endmodule
仿真波形