原创 FSM 状态机模板

-- This is a sample state-machine using enumerated types.
-- This will allow the synthesis tool to select the appropriate
-- encoding style and will make the code more readable.
 
--Insert the following in the architecture before the begin keyword
   --Use descriptive names for the states, like st1_reset, st2_search
   type state_type is (st1_<name_state>, st2_<name_state>, ...);
   signal state, next_state : state_type;
   --Declare internal signals for all outputs of the state-machine
   signal <output>_i : std_logic;  -- example output signal
   --other outputs
 
--Insert the following in the architecture after the begin keyword
   SYNC_PROC: process (<clock>)
   begin
      if (<clock>'event and <clock> = '1') then
         if (<reset> = '1') then
            state <= st1_<name_state>;
            <output> <= '0';
         else
            state <= next_state;
            <output> <= <output>_i;
         -- assign other outputs to internal signals
         end if;       
      end if;
   end process;
 
   --MOORE State-Machine - Outputs based on state only
   OUTPUT_DECODE: process (state)
   begin
      --insert statements to decode internal output signals
      --below is simple example
      if state = st3_<name> then
         <output>_i <= '1';
      else
         <output>_i <= '0';
      end if;
   end process;
 
   --MEALY State-Machine - Outputs based on state and inputs
   OUTPUT_DECODE: process (state, <input1>, <input2>, ...)
   begin
      --insert statements to decode internal output signals
      --below is simple example
      if (state = st3_<name> and <input1> = '1') then
         <output>_i <= '1';
      else
         <output>_i <= '0';
      end if;
   end process;

   NEXT_STATE_DECODE: process (state, <input1>, <input2>, ...)
   begin
      --declare default state for next_state to avoid latches
      next_state <= state;  --default is to stay in current state
      --insert statements to decode next_state
      --below is a simple example
      case (state) is
         when st1_<name> =>
            if <input_1> = '1' then
               next_state <= st2_<name>;
            end if;
         when st2_<name> =>
            if <input_2> = '1' then
               next_state <= st3_<name>;
            end if;
         when st3_<name> =>
            next_state <= st1_<name>;
         when others =>
            next_state <= st1_<name>;
      end case;     
   end process;

   <FSM_NAME>_SYNC_PROC: process (<clock>)
   begin
      if (<clock>'event and <clock> = '1') then
         if (<reset> = '1') then
            <fsm>_state <= st1_<name_state>;
            -- Output signals here will have one clock delay of the <state> ( outputx by state )
            <output1> <= '0';
            <output2> <= '0';

         else
            <fsm>_state <= <fsm>_next_state;
            <output1> <= <output1>_c;
            <output2> <= <output2>_c;

         -- assign other outputs to internal signals

         end if;        
      end if;
   end process;


   <FSM_NAME>_NEXT_STATE_DECODE: process (<fsm>_state, <input1>, <input2>, ...)
   begin
      --declare default state for next_state to avoid latches
      <fsm>_next_state <= <fsm>_state;  
      -- default is to stay in current state
      -- so there are no else branch in the if statement
      case (<fsm>_state) is
         when <fsm>_st1_<name> =>
            -- State Change Condition
            if <input_1> = '1' then
               <fsm>_next_state <= <fsm>_st2_<name>;
               -- Internal Output can put here
               -- Only occur on state transaction (next_state changed but state not changed)
               -- If output need to assert at first cycle of one state,
               -- we can delay this output one clock in <FSM_NAME>_SYNC_PROC process
            end if;
            -- Internal Output can put here
            -- This output will be asserted till state change

         when <fsm>_st2_<name> =>
            if <input_2> = '1' then
               <fsm>_next_state <= <fsm>_st3_<name>;
            end if;
         when <fsm>_st3_<name> =>
            <fsm>_next_state <= <fsm>_st1_<name>;
         when others =>
            <fsm>_next_state <= <fsm>_st1_<name>;
      end case;      
   end process;

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    21:59:36 03/11/2009
-- Design Name:
-- Module Name:    FSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FSM is
    Port ( Input1 : in  STD_LOGIC;
           Input2 : in  STD_LOGIC;
           Input3 : in  STD_LOGIC;
     
           Output1 : out  STD_LOGIC;
           Output2 : out  STD_LOGIC;
           Output3 : out  STD_LOGIC;
     
           FSM_CLK : in  STD_LOGIC;
           FSM_RST : in  STD_LOGIC);
end FSM;

architecture Behavioral of FSM is

-- This is a sample current_state-machine using enumerated types.
-- This will allow the synthesis tool to select the appropriate
-- encoding style and will make the code more readable.
 
-- Insert the following in the architecture before the begin keyword

   -- Use descriptive names for the states, like st1_reset, st2_search
   type state_type is (st1, st2, st3);
  
   -- Declare current and next state signals
  signal current_state, next_state : state_type;
  
   -- State vector declaration
   ATTRIBUTE state_vector : string;
   ATTRIBUTE state_vector OF Behavioral : architecture IS "current_state" ;

  -- Declare internal signals for all outputs of the state machine
   -- Declare any pre-registered internal signals
   signal Output1_i : std_logic;  -- example output signal
   signal Output2_i : std_logic;  -- example output signal
   signal Output3_i : std_logic;  -- example output signal
 
   -- other internal outputs
  signal Int_Output1 : std_logic;
  signal Int_Output2 : std_logic;
  signal Int_Output3 : std_logic;
 
begin

--Insert the following in the architecture after the begin keyword
   --ASYNC_PROC: process (FSM_CLK, FSM_RST)
   SYNC_PROC: process (FSM_CLK)
   begin
      -- if (FSM_RST = '1') then
     
      if (FSM_CLK'event and FSM_CLK = '1') then
         if (FSM_RST = '1') then
            current_state <= st1;

            -- Default Reset Values for all outputs of the state machine
            Output1 <= '0';
            Output2 <= '0';
            Output3 <= '0';
      
            -- Default Reset Values for all other internal outputs
            Int_Output1 <= '0';
            Int_Output2 <= '0';
            Int_Output3 <= '0';
      
    --elsif (FSM_CLK'event and FSM_CLK = '1') then
    else
            current_state <= next_state;
      
      -- Registered output assignments for all outputs of the state machine      
            Output1 <= Output1_i;
            Output2 <= Output2_i;
            Output3 <= Output3_i;
           
      -- Default Assignment To all other internal outputs
            Int_Output1 <= Int_Output1;
            Int_Output2 <= Int_Output2;
            Int_Output3 <= Int_Output3;
      
            -- State Actions for internal signals only -- Int_Output1, Int_Output2
      case current_state is
       when st1 =>
         Int_Output1 <= Input2;
        
       when st2 =>
         Int_Output2 <= Input3;
        
       when others =>
        null;
        
      end case;

      -- Transition Actions for internal signals only -- Int_Output3
      case current_state is
       when st1 =>
        if ( Int_Output3 = '1' ) then
         Int_Output3 <= '0';
        end if;
        
       when st2 =>
        if ( Input3 = '1' ) then
         Int_Output3 <= '1';
        end if;
        
       when others =>
        null;
        
      end case;

    
         end if;       
      end if;
   end process;

  --MEALY State-Machine - Outputs based on current_state and inputs
  --OUTPUT_DECODE_MEALY: process (current_state, input1, input2, input3)
 
    --MOORE State-Machine - Outputs based on current_state only
   OUTPUT_DECODE_MOORE: process (current_state)
   begin
   
      -- Default Assignment for any pre-registered internal signals
   Output1_i <= '0';
   Output2_i <= '0';
   Output3_i <= '0';
     
      -- Default Assignment for other internal outputs
   Int_Output1 <= '0';
   Int_Output2 <= '0';
   Int_Output3 <= '0';
   
     
      -- Assignment for any pre-registered internal signals
      -- Assignment for other internal outputs
   
   ----------------------------------------------------------------------------------
      --below is simple example 1
   ----------------------------------------------------------------------------------
      case (current_state) is
         when st1 =>
     -- if ( Input1 = '1' ) then
      Output1_i <= '1';
      Int_Output1 <= '0';
     -- end if;
     
         when st2 =>
      Output2_i <= '1';
      Int_Output2 <= '0';
      
         when st3 =>
      Output3_i <= '1';
      
         when others =>
     null;
      
      end case;     

   ----------------------------------------------------------------------------------
      --below is simple example 2
   ----------------------------------------------------------------------------------
      if current_state = st1 then
         Output1_i <= '1';
         Int_Output1 <= '1';
      else
         Output1_i <= '0';
         Int_Output1 <= '0';
      end if;
   
      if current_state = st2 then
         Output2_i <= '1';
         Int_Output2 <= '1';
      else
         Output2_i <= '0';
         Int_Output2 <= '0';
      end if;

      if current_state = st3 then
         Output3_i <= '1';
      else
         Output3_i <= '0';
      end if;
   
   end process;

   NEXT_STATE_DECODE: process (current_state, Input1, Input2, Input3)
   begin
      --declare default current_state for next_state to avoid latches
      next_state <= current_state;  --default is to stay in current current_state
   
      --insert statements to decode next_state
      case (current_state) is
         when st1 =>
            if input1 = '1' then
               next_state <= st2;
            end if;
      
         when st2 =>
            if input2 = '1' then
               next_state <= st3;
            end if;
      
         when st3 =>
      if input3 = '1' then
       next_state <= st1;
      end if;
      
         when others =>
            next_state <= st1;
      
      end case;     
   end process;

    
end Behavioral;