原创 verilog array pack/unpack

 2020-2-12 11:03  3217 12 2 分类: FPGA/CPLD 文集: FPGA/verilog

/**********************************************************************************************************************************/

`define ASSIGN_UNPACK_ARRAY(PK_LEN, PK_WIDTH, UNPK_DEST, PK_SRC)
wire [PK_LEN*PK_WIDTH-1:0] PK_IN_BUS;

assign PK_IN_BUS=PK_SRC;
generate
genvar unpk_idx;
for (unpk_idx=0; unpk_idx
gen_unpack assign UNPK_DEST[unpk_idx][PK_WIDTH-1:0]=PK_IN_BUS[PK_WIDTH*unpk_idx+:PK_WIDTH];
end
endgenerate

/**********************************************************************************************************************************/

`define PACK_ARRAY(PK_LEN, PK_WIDTH, UNPK_SRC) PK_OUT_BUS；

wire [PK_LEN*PK_WIDTH-1:0] PK_OUT_BUS;

generate

genvar pk_idx;

for (pk_idx=0; pk_idx

gen_pack assign PK_OUT_BUS[PK_WIDTH*pk_idx+:PK_WIDTH]=UNPK_SRC[pk_idx][PK_WIDTH-1:0];

end

endgenerate

/**********************************************************************************************************************************/

PK_IN_BUS[PK_WIDTH*unpk_idx+:PK_WIDTH]

PK_OUT_BUS[PK_WIDTH*pk_idx+:PK_WIDTH]

indexed part-select：

x +: N, The start position of the vector is given by x and you count up from x by N.

There is also

x -: N, in this case the start position is x and you count down from x by N.

N is a constant and x is an expression that can contain iterators.

/**********************************************************************************************************************************/

more:https://www.movit.top/2020/02/7400-verilog-hdl.html

/**********************************************************************************************************************************/

作者： MOVIT，来源：面包板社区