原创 ARM7TDMI CORE Technical Reference Manual 1

2007-10-28 09:46 1925 3 3 分类: 工程师职场

1.1 About the ARM7TDMI core
The ARM7TDMI core is a member of the ARM family of general-purpose 32-bit
microprocessors. The ARM family offers high performance for very low power
consumption, and small size.
The ARM architecture is based on Reduced Instruction Set Computer (RISC)
principles. The RISC instruction set and related decode mechanism are much simpler
than those of Complex Instruction Set Computer (CISC) designs. This simplicity gives:
* a high instruction throughput
* an excellent real-time interrupt response
* a small, cost-effective, processor macrocell.


1.1.1 The instruction pipeline
The ARM7TDMI core uses a pipeline to increase the speed of the flow of instructions
to the processor. This enables several operations to take place simultaneously, and the
processing and memory systems to operate continuously.
A three-stage pipeline is used, so instructions are executed in three stages:
* Fetch
* Decode
* Execute.
The instruction pipeline is shown in Figure 1-1.


During normal operation, while one instruction is being executed, its successor is being
decoded, and a third instruction is being fetched from memory.
The program counter points to the instruction being fetched rather than to the instruction
being executed. This is important because it means that the Program Counter (PC)
value used in an executing instruction is always two instructions ahead of the address.


1.1.2 Memory access
The ARM7TDMI core has a Von Neumann architecture, with a single 32-bit data bus
carrying both instructions and data. Only load, store, and swap instructions can access
data from memory.
Data can be:
* 8-bit (bytes)
* 16-bit (halfwords)
* 32-bit (words).
Words must be aligned to 4-byte boundaries. Halfwords must be aligned to 2-byte
boundaries.


1.1.3 Memory interface
The ARM7TDMI processor memory interface has been designed to allow performance
potential to be realized, while minimizing the use of memory. Speed-critical control
signals are pipelined to enable system control functions to be implemented in standard
low-power logic. These control signals facilitate the exploitation of the fast-burst access
modes supported by many on-chip and off-chip memory technologies.
The ARM7TDMI core has four basic types of memory cycle:
* idle cycle
* nonsequential cycle
* sequential cycle
* coprocessor register transfer cycle.


1.1.4 EmbeddedICE-RT logic
The EmbeddedICE-RT logic provides integrated on-chip debug support for the
ARM7TDMI core. You use the EmbeddedICE-RT logic to program the conditions
under which a breakpoint or watchpoint can occur.
The EmbeddedICE-RT logic contains a Debug Communications Channel (DCC), used
to pass information between the target and the host debugger. The EmbeddedICE-RT
logic is controlled through the Joint Test Action Group (JTAG) test access port.


1.2 Architecture
The ARM7TDMI processor has two instruction sets:
* the 32-bit ARM instruction set
* the 16-bit Thumb instruction set.
The ARM7TDMI processor is an implementation of the ARMv4T architecture. For full
details of both the ARM and Thumb instruction sets, see the ARM Architecture
Reference Manual.
This section describes:
* Instruction compression
* The Thumb instruction set.


1.2.1 Instruction compression
Microprocessor architectures traditionally have the same width for instructions and
data. In comparison with 16-bit architectures, 32-bit architectures exhibit higher
performance when manipulating 32-bit data, and can address a large address space
much more efficiently.
16-bit architectures typically have higher code density than 32-bit architectures, but
approximately half the performance.
Thumb implements a 16-bit instruction set on a 32-bit architecture to provide:
* higher performance than a 16-bit architecture
* higher code density than a 32-bit architecture.


1.2.2 The Thumb instruction set
The Thumb instruction set is a subset of the most commonly used 32-bit ARM
instructions. Thumb instructions are each 16 bits long, and have a corresponding 32-bit
ARM instruction that has the same effect on the processor model. Thumb instructions
operate with the standard ARM register configuration, allowing excellent
interoperability between ARM and Thumb states.
On execution, 16-bit Thumb instructions are transparently decompressed to full 32-bit
ARM instructions in real time, without performance loss.
Thumb has all the advantages of a 32-bit core:
* 32-bit address space
* 32-bit registers
* 32-bit shifter, and Arithmetic Logic Unit (ALU)
* 32-bit memory transfer.


Thumb therefore offers a long branch range, powerful arithmetic operations, and a large
address space.
Thumb code is typically 65% of the size of ARM code, and provides 160% of the
performance of ARM code when running from a 16-bit memory system. Thumb,
therefore, makes the ARM7TDMI core ideally suited to embedded applications with
restricted memory bandwidth, where code density and footprint is important.
The availability of both 16-bit Thumb and 32-bit ARM instruction sets gives designers
the flexibility to emphasize performance or code size on a subroutine level, according
to the requirements of their applications. For example, critical loops for applications
such as fast interrupts and DSP algorithms can be coded using the full ARM instruction
set then linked with Thumb code.


1.3 Block, core, and functional diagrams
The ARM7TDMI processor architecture, core, and functional diagrams are illustrated
in the following figures:
* Figure 1-2 on page 1-8 shows a block diagram of the ARM7TDMI processor
components and major signal paths
* Figure 1-3 on page 1-9 shows the main processor logic at the core of the
ARM7TDMI
* Figure 1-4 on page 1-10 shows the major signal paths for the ARM7TDMI
processor.


1.4 Instruction set summary
This section provides a description of the instruction sets used on the ARM7TDMI
processor.
This section describes:
* Format summary
* ARM instruction summary on page 1-13
* Thumb instruction summary on page1-20.
1.4.1 Format summary
This section provides a summary of the ARM, and Thumb instruction sets:
* ARM instruction summary on page 1-13
* Thumb instruction summary on page1-20.
A key to the instruction set tables is provided in Table 1-1.
The ARM7TDMI processor uses an implementation of the ARMv4T architecture. For
a complete description of both instruction sets, see the ARM Architecture Reference
Manual.

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