原创 创芯Xilinx Microblaze 学习系列第三集

用创芯SOC开发板设计的效果

超级终端

显示

#include "stdio.h"
#include "xgpio.h"
#include "xparameters.h"
#include "xio.h"
#include "xil_types.h"

XGpio   led_gpio;
int main()
{
 int i;

  Xuint32 Mystatus ;

  //初始化
  Mystatus=XGpio_Initialize(&led_gpio,XPAR_AXI_GPIO_0_DEVICE_ID);
  XGpio_SetDataDirection(&led_gpio,1,0);
  while(1)
  {
  XGpio_DiscreteWrite(&led_gpio,1,0x1);
  for(i=100; i>0; i--)
  xil_printf("-- %D ChuangXin SOC Board Test --\n\r",i);
  XGpio_DiscreteWrite(&led_gpio,1,0x2);
  for(i=100; i>0; i--)
  xil_printf("-- %D ChuangXin SOC Board Test  --\n\r",i);
  }
  
}

MHS文件

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.2 Build EDK_O.61xd
# Sun Jul 07 11:43:10 2013
# Target Board:  Custom
# Family:    spartan6
# Device:    xc6slx9
# Package:   tqg144
# Speed Grade:  -3
# ##############################################################################
 PARAMETER VERSION = 2.1.0

 PORT rst = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 0
 PORT clk_in = CLK, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT uart_rx = axi_uartlite_0_RX, DIR = I
 PORT uart_tx = axi_uartlite_0_TX, DIR = O
 PORT led_gpio = axi_gpio_0_GPIO_IO_O, DIR = O, VEC = [1:0]

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
 PORT MB_Reset = proc_sys_reset_0_MB_Reset
 PORT Slowest_sync_clk = clk_50_0000MHz
 PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
 PORT Ext_Reset_In = RESET
 PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_ilmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_50_0000MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = microblaze_0_ilmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_dlmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_50_0000MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = microblaze_0_dlmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN bram_block
 PARAMETER INSTANCE = microblaze_0_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
 BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 8.20.a
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0X00000000
 PARAMETER C_ICACHE_HIGHADDR = 0X3FFFFFFF
 PARAMETER C_USE_ICACHE = 0
 PARAMETER C_ICACHE_ALWAYS_USED = 0
 PARAMETER C_DCACHE_BASEADDR = 0X00000000
 PARAMETER C_DCACHE_HIGHADDR = 0X3FFFFFFF
 PARAMETER C_USE_DCACHE = 0
 PARAMETER C_DCACHE_ALWAYS_USED = 0
 BUS_INTERFACE ILMB = microblaze_0_ilmb
 BUS_INTERFACE DLMB = microblaze_0_dlmb
 BUS_INTERFACE M_AXI_DP = axi4lite_0
 BUS_INTERFACE DEBUG = microblaze_0_debug
 PORT MB_RESET = proc_sys_reset_0_MB_Reset
 PORT CLK = clk_50_0000MHz
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_UART = 1
 PARAMETER C_BASEADDR = 0x74800000
 PARAMETER C_HIGHADDR = 0x7480ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
 PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT S_AXI_ACLK = clk_50_0000MHz
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 4.02.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 50000000
 PARAMETER C_CLKOUT0_GROUP = NONE
 PORT LOCKED = proc_sys_reset_0_Dcm_locked
 PORT CLKOUT0 = clk_50_0000MHz
 PORT RST = RESET
 PORT CLKIN = CLK
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT interconnect_aclk = clk_50_0000MHz
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_uartlite
 PARAMETER INSTANCE = axi_uartlite_0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_50_0000MHz
 PORT RX = axi_uartlite_0_RX
 PORT TX = axi_uartlite_0_TX
END

BEGIN axi_gpio
 PARAMETER INSTANCE = axi_gpio_0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_GPIO_WIDTH = 2
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_50_0000MHz
 PORT GPIO_IO_O = axi_gpio_0_GPIO_IO_O
END

约束文件

NET fpga_clk  LOC = "P56" ;
NET fpga_rst  LOC = "P57" ;
NET led[0] LOC = "P83" ;
NET led[1] LOC = "P82" ;
NET led[2] LOC = "P81" ;
NET led[3] LOC = "P80" ;
NET uart_rx  LOC = "P112" ;
NET uart_tx  LOC = "P111" ;

ISE文件

`timescale 1ns / 1ps

module cx_demo_top(
            fpga_clk,
            fpga_rst,
           
            led,
            uart_rx,
            uart_tx
            );

 input fpga_clk;
 input fpga_rst;
 input  uart_rx;
 output uart_tx;
 output [3:0]led;
 
 wire clk100;
 wire rst;
 clk_gen U1_CLK_GEN(
                     //input   
                     .fpga_din(fpga_clk),
                     .fpga_rst(fpga_rst), 
                     //output     
                     .clk100  (clk100  ),     
                     .rst     (rst     )           
                     );

 wire  [1:0] led_mb;
 (* BOX_TYPE = "user_black_box" *)
 microblaze U_CPU (
                  .rst    (~rst      ),
                  .clk_in (clk100   ),
                  .uart_rx(uart_rx  ),
                  .uart_tx(uart_tx  ),
                  .led_gpio(led_mb  )
                  );

 reg [9:0] cnt;initial cnt = 10'd0;
 always @(posedge fpga_clk)
 cnt <= cnt + 1'b1;
 assign led = {1'b0,cnt[9],led_mb};

endmodule
 

`timescale 1ns / 10ps
module clk_gen(
               //input   
               fpga_din,
               fpga_rst,
                         
               //output     
               clk100,  
                      
               rst,           
              );
  //IO defination
 
  input  fpga_din;
  input  fpga_rst  ;
 

  output clk100; 

  output rst;

  wire rst_ff16;
  SRL16E #(.INIT(16'h0000))
  U_SRL16(
          .Q(rst_ff16),
          .A0(1'b1),
          .A1(1'b1),
          .A2(1'b1),
          .A3(1'b1),
          .CLK(fpga_din),
          .CE(1'd1),
          .D(fpga_rst)
          );
 
  reg rst_tmp;
 
  always @ (posedge fpga_din)
    begin
       rst_tmp <= fpga_rst & rst_ff16;
    end 
       
  wire lock;                   
  dcm U1_DCM
   (// Clock in ports
    .clk_in(fpga_din),      // IN
    // Clock out ports
    .clk100(clk100),     // OUT
    // Status and control signals
    .rst(rst_tmp),// IN
   
    .locked(lock));      // OUT           
  wire rst;
  assign rst = ~lock;

  reg led;
  always @ (posedge clk100)
  begin
     led <= lock;
  end
   
endmodule