presentation of DDR design considerationDDR System Design Considerations Integrated Technology Group Micron 1 DDR Overview 2 SSTL2 Signal Levels Driver Receiver December, 00 3 SSTL2 Double Ended Termination VTTTermination Island VTT/VREF Generator SSTL_2 Address/Cmnd Chip Selects PC266 SDRAM Reg. DIMM Chipset “North Bridge” SSTL_2 PC266 SDRAM Reg. DIMM Address / Command VTT Termination Island Data/Strobe/Mask December, 00 4 SSTL2 Single Ended Termination VTT/VREF Generator SSTL_2 Address/Cmnd Chip Selects Chipset “North Bridge” SSTL_2 PC266 SDRAM Reg. DIMM PC266 SDRAM Reg. DIMM Address/Command VTT Termination Island Data/Strobe/Mask December, 00 5 Use Single Parallel Termination Resistor With Series Resistor m Lower system cost m Easier motherboard route m Improved bandwidth m Lower skew due t……