PS:Xilinx Spartan 3E Starter Kit平台上LCD1602与板载Intel Flash Memory公用四根数据线,读写命令和数据时分别写高四位和低四位,具体请查阅三楼的数据手册源码:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity LCD1602 is Port ( CLK : in std_logic; Reset : in std_logic; LCD_RS : out std_logic; LCD_RW : out std_logic; LCD_EN : out std_logic; data : out std_logic_vector(3 downto 0));end LCD1602;architecture Behavioral of LCD1602 is type iState is ( Write_instr, --写命令字 Write_DataUP4_1, --写LCD一线高4位 Write_DataDown4_1, --写LCD一线低4位 Set_DDRamAddUp, --设置DDRam地址高4位 Set_DDRamAddDown, --设置DDRam地址低4位 Write_DataUP4_2, --写LCD二线高4位 Write_DataDown4_2 --写LCD二线低4位 ); signal State:iState; type Ram is array(0 to 15) of std_logic_vector(7 downto 0); constant MyRamUp:Ram:=(x"46",x"68",x"69",x"73",x"20",x"49",x"73",x"20",x"4d",x"79",x"20",x"46",x"69",x"72",x"73",x"74"); --This Is My First constant MyRamDown:Ram:=(x"20",x"20",x"46",x"50",x"47",x"41",x"20",x"50",x"72",x"6f",x"67",x"72",x"61",x"6d",x"20",x"20"); --FPGA Program signal LCD_Clk : std_logic :='0'; signal datacnt : integer range 0 to 15:=0; begin LCD_RW = '0'; LCD_EN = LCD_Clk; process(CLK) --20000分频,满足时序要求 variable n1:integer range 0 to 19999;begin if rising_edge(CLK) then if n119999 then n1:=n1+1; else n1:=0; LCD_Clk=not LCD_Clk; end if; end if;end process;process(LCD_Clk,state,reset)begin if Reset='0' then state=Write_instr; LCD_RS = '0'; elsif rising_edge(LCD_Clk) then case state is when Write_instr=> --写命令字到LCD控制器 LCD_RS='0'; if(datacnt=0)then data="0011"; --0011 datacnt=datacnt+1; elsif(datacnt=1)then data="0011"; --0011 datacnt=datacnt+1; elsif(datacnt=2)then data="0011"; --0011 datacnt=datacnt+1; elsif(datacnt=3)then data="0010"; --0010 datacnt=datacnt+1; elsif(datacnt=4)then --0x28 : 0010 1000 =>功能设置 data="0010"; datacnt=datacnt+1; elsif(datacnt=5)then data="1000"; datacnt=datacnt+1; elsif(datacnt=6)then --0x06 : 0000 0110 =>模式设定 data="0000"; datacnt=datacnt+1; elsif(datacnt=7)then data="0110"; datacnt=datacnt+1; elsif(datacnt=8)then --0x0c : 0000 1100 =>显示设定 data="0000"; datacnt=datacnt+1; elsif(datacnt=9)then data="1100"; datacnt=datacnt+1; elsif(datacnt=10)then --0x10 : 1000 0000 =>00H 设定读写地址位 data="1000"; datacnt=datacnt+1; else data="0000"; datacnt=0; state=Write_DataUP4_1; end if; when Write_DataUP4_1=> LCD_RS='1'; data = MyRamUp(datacnt)(7 downto 4); state = Write_DataDown4_1; when Write_DataDown4_1=> if datacnt=15 then data = MyRamUp(datacnt)(3 downto 0); datacnt=0; state =Set_DDRamAddUp; else data = MyRamUp(datacnt)(3 downto 0); datacnt=datacnt+1; state =Write_DataUP4_1; end if; when Set_DDRamAddUp=> --0xc0 : 1100 0000=>40H 设定读写地址位 LCD_RS='0'; data="1100"; state=Set_DDRamAddDown; when Set_DDRamAddDown=> data="0000"; state=Write_DataUP4_2; when Write_DataUP4_2=> LCD_RS='1'; data = MyRamDown(datacnt)(7 downto 4); state = Write_DataDown4_2; when Write_DataDown4_2=> if datacnt=15 then data = MyRamDown(datacnt)(3 downto 0); datacnt=0; state =Write_DataUP4_1; else data = MyRamDown(datacnt)(3 downto 0); datacnt=datacnt+1; state =Write_DataUP4_2; end if; when others=> state=Write_instr; end case; end if;end process;end Behavioral;……