针对于Virtex5 FPGA的DDR2读写测试的完整工程，2颗DDR2芯片的数据总线并接为32位，时钟200MHzisefile.......\.HDI-PlanAhead-1664-32af18fdc96e467.......\...................................\ngc2edif.......\...................................\........\_xmsgs.......\...................................\........\......\ngc2edif.xmsgs.......\...................................\........\ngc2edif.log.......\TS112_pcie.gise.......\TS112_pcie.sdc.......\TS112_pcie.xdl.......\TS112_pcie.xise.......\TS112_pcie_bitgen.xwbt.......\TS112_pcie_guide.ncd.......\TS112_pcie_summary.html.......\_verilog_hintfile.......\_xmsgs.......\......\ngc2edif.xmsgs.......\......\ngcbuild.xmsgs.......\......\xdl.xmsgs.......\a64_128_distram_fifo.ngc.......\a64_64_distram_fifo.ngc.......\addr_cntrl_fifo.ngc.......\cdc.cdc.......\data_trn_mem_fifo.ngc.......\ddr2_ip_summary.html.......\dualport_32x32_compram.ngc.......\ediftop.lmp.......\ediftop_ngc0.srs.......\ediftop_ngc1.srs.......\ediftop_ngc2.srs.......\ediftop_ngc3.srs.......\ediftop_ngc4.srs.......\ediftop_ngc5.srs.......\ediftop_ngc_nocompress0.srs.......\ediftop_ngc_nocompress1.srs.......\ediftop_ngc_nocompress2.srs.......\ediftop_ngc_nocompress3.srs.......\ediftop_ngc_nocompress4.srs.......\ediftop_ngc_nocompress5.srs.......\ipcore_dir.......\iseconfig.......\.........\TS112_pcie.projectmgr.......\.........\TS112_pcie.xreport.......\ngc2edif.log.......\pa.fromHdl.tcl.......\pa.fromNcd.tcl.......\pa.fromNetlist.tcl.......\planAhead.ngc2edif.log.......\verilog.tbl.......\vhdl.tbl.......\vhdlcfg.tbl.......\xfer_trn_mem_fifo.ngcsrc...\TS112_pcie.ucf...\TS112_pcie.v...\TS112_pcie.vhd...\TS112_pcie.vhd.bak...\ajiu...\....\bus_mux.v...\....\conv64_2_128.v...\....\ctrlreg.v...\....\data10b_64b.vhd...\....\data64b_10b.vhd...\....\data_mux.vhd...\....\data_wide_change.vhd...\....\ddr2_ctrl1.vhd...\....\ddr2_ctrl_mmu.vhd...\....\ddr2_ctrl_mmu_bak.vhd...\....\ddr2_in_test.vhd...\....\ddr2_out_test.vhd...\....\ddra_ctrl.vhd...\....\fifo_128_1k.vhd...\....\fifo_160_1k.vhd...\....\fifo_32_1k.vhd...\....\fifo_32_256.vhd...\....\fifo_4x4096.vhd...\....\fifo_64_256.vhd...\....\ip_core...\....\.......\_xmsgs...\....\.......\......\pn_parser.xmsgs...\....\.......\fifo_4x4096.asy...\....\.......\fifo_4x4096.gise...\....\.......\fifo_4x4096.ncf...\....\.......\fifo_4x4096.ngc...\....\.......\fifo_4x4096.v...\....\.......\fifo_4x4096.veo...\....\.......\fifo_4x4096.vhd...\....\.......\fifo_4x4096.vho...\....\.......\fifo_4x4096.xco...\....\.......\fifo_4x4096.xise...\....\.......\fifo_4x4096_flist.txt...\....\.......\fifo_4x4096_xmdf.tcl...\....\sdi_data_gen.vhd...\....\sdi_pcie_top.vhd...\ddr2...\....\_xmsgs...\....\......\pn_parser.xmsgs...\....\coregen.cgc...\....\coregen.cgp...\....\ddr2_ip...\....\.......\docs……