INTRODUCTION 1.1 ETHERNET IP CORE INTRODUCTION1.2 ETHERNET IP CORE FEATURES1.3 ETHERNET IP CORE DIRECTORY STRUCTURE ETHERNET MAC IP CORE2.1 OVERVIEW 2.1.1 WISHBONE Interface2.1.2 Transmit Module2.1.3 Receive Module2.1.4 Control Module 2.1.5 MII Module (Media Independent Module)2.1.6 Status Module 2.1.7 Register Module 2.2 CORE FILE HIERARCHY 2.3 DESCRIPTION OF CORE MODULES 2.3.1 Description of the MII module (eth_miim.v)2.3.2 Description of the Receive module (eth_rxethmac.v)2.3.3 Description of the Transmit module (eth_txethmac.v) 2.3.4 Description of the Control module (eth_maccontrol.v)2.3.5 Description of the Status module (eth_macstatus.v)2.3.6 Description of the Registers module (eth_registers.v) 2.3.7 Description of the WISHBONE interface module (eth_wishbone.v) ETHERNET MAC IP CORE TESTBENCH 3.1 OVERVIEW 3.2 TESTBENCH FILE HIERARCHY3.2.1 Testbench Module Hierarchy3.3 DESCRIPTION OF TESTBENCH MODULES 3.3.1 Description of Ethernet PHY module3.3.2 Description of WB submodules 3.4 DESCRIPTION OF TESTCASES 3.4.1 Description of MAC Registers and BD Tests3.4.2 Description of MIIM Module Tests……