蜂鸣器报警/*-------------------------------------------------------- -- Engineer: zhrscut -- Create Date: -- Module Name: -- Tool Versions: Quartus_II 9.1 -- 欢迎加入 EEPW ，FPGA 开发板 DIY 活动 --------------------------------------------------------*/ module beep(clk,beep); input clk; output beep; reg[21:0] cnt; always @(posedge clk ) if(cnt else cnt assign beep=(cnt endmodule ……