The Direct Memory Access Controller (DMA) is designed to service high-data-throughput periph-
erals operating on the SFR bus, allowing them to access data memory directly and eliminating
the need for CPU-intensive management. By allowing these data-intensive peripherals to share
their own data path, the main data bus is also off-loaded, resulting in additional power savings.
The DMA Controller has these features:
• Multiple independent and independently-programmable channels
• Concurrent operation with the CPU (no DMA-caused wait states)
• DMA bus arbitration
• Five Programmable address modes
• Four Programmable transfer modes
• Four Flexible internal data transfer modes
• Byte or word support for data transfer
• 16-bit source and destination address register for each channel, dynamically updated and
reloadable
• 16-bit transaction count register, dynamically updated and reloadable
• Upper and lower address limit registers
• Counter half-full level interrupt
• Software-triggered transfer Section 54. Direct Memory Access Controller (DMA)
HIGHLIGHTS
This section of the manual contains the following major topics:
54.1 Introduction ................................................................................................................. 54-2
54.2 Registers ..................................................................................................................... 54-4
54.3 Data Transfers Options ............................................................................................... 54-8
54.4 Channel Priority and Priority Schemes ...................................................................……
