【应用手册】Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines Low-cost FPGAs designed on 90-nm and 65-nm process technologies are made to support high performance applications with system clocks and interfaces such as DDR2 pushing 200 MHz and LVDS applications up to 840 Mbps. The device is designed with fast edge rates which can cause signal integrity problems such as simultaneous switching noise (SSN) which may limit system performance and affect circuit operation. These problems can exist even at low data rates as the signal edge rate remains the same regardless of the data rate. For high performance applications such as DDR2 interfaces, Altera® has largely done the work by preassigning DQ and DQS signals and accounting for SSN when setting performance limits. For other applications, it is up to the designer to determine the pin placement and I/O settings to optimize performance. By following some simple guidelines and best practices for device settings, pin-out selection, and PCB design, you can avoid many of the signal integrity problems for your designs. This application note provides a framework to describe SSN and understand the sources of SSN, discusses ways to mitigate SSN for Cyclone® III FPGAs by using I/O settings and selecting proper I/O standards, and provides guidelines on PCB design that are good practice for general high speed digital designs. To demonstrate the effects of the various recommendations, characterization data measured on Cyclone III devices is shown throughout. Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines December 2007, ver. 1.0 Application Note 508 Introduction Low-cost FPGAs designed on 90-nm and 65-nm process technologies are made to support high performance applications with system clocks and interfaces such as DDR2 pushing 200 MHz and LVDS applications up to 840 Mbps. The device is designed with fast edge rates which can cause signal integrity problems such as simultaneous switching noise (SSN) ……