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【应用手册】RapidIO Interoperability with TI 6482 DSP Reference Design
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时间:2019-12-24
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【应用手册】RapidIO Interoperability with TI 6482 DSP Reference Design The Altera® RapidIO interoperability reference design provides a sample interface between the Altera RapidIO MegaCore® function and the Texas Instruments TMS320TCI6482 Communications Infrastructure Digital Signal Processor (TI 6482 DSP or TI 6482). Altera offers this reference design to demonstrate the installation and operation of Altera’s RapidIO MegaCore function with the TI 6482. The reference design enables you to evaluate the RapidIO MegaCore function for integration into an Altera FPGA. In addition to demonstrating basic interoperability, the design includes support to measure link utilization in all modes, at all data rates, for all supported packet sizes. The statistics support helps you to determine the optimal payload size for transfers across the Serial RapidIO link from the Stratix® II GX device to the TI 6482 DSP, given a set of operating constraints such as lane width and baud rate. RapidIO Interoperability with TI 6482 DSP Reference Design November 2008 AN513-2.0 Introduction The Altera RapidIO interoperability reference design provides a sample interface between the Altera RapidIO MegaCore function and the Texas Instruments TMS320TCI6482 Communications Infrastructure Digital Signal Processor (TI 6482 DSP or TI 6482). Altera offers this reference design to demonstrate the installation and operation of Altera’s RapidIO MegaCore function with the TI 6482. ……
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