资料
  • 资料
  • 专题
【应用手册】General-Purpose PLLs in Stratix & Stratix GX Devices
推荐星级:
时间:2019-12-24
大小:670.5KB
阅读数:240
上传用户:16245458_qq.com
查看他发布的资源
下载次数
0
所需E币
4
ebi
新用户注册即送 300 E币
更多E币赚取方法,请查看
close
资料介绍
【应用手册】General-Purpose PLLs in Stratix & Stratix GX Devices Stratix® and Stratix GX devices have highly versatile phase-locked loops (PLLs) that provide robust clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces. There are two types of PLLs in each Stratix and Stratix GX device: enhanced PLLs and fast PLLs. Each device has up to four enhanced PLLs, which are feature-rich, general-purpose PLLs supporting advanced capabilities such as external feedback, clock switchover, phase and delay control, PLL reconfiguration, spread spectrum clocking, and programmable bandwidth. There are also up to eight fast PLLs per device, which offer general-purpose clock management with multiplication and phase shifting as well as high-speed outputs to manage the high-speed differential I/O interfaces. The Altera® Quartus® II software enables the PLLs and their features without requiring any external devices. 1. General-Purpose PLLs in Stratix & Stratix GX Devices S52001-3.2 Introduction Stratix and Stratix GX devices have highly versatile phase-locked loops (PLLs) that provide robust clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces. There are two types of PLLs in each Stratix and Stratix GX device: enhanced PLLs and fast PLLs. Each device has up to four enhanced PLLs, which are feature-rich, general-purpose PLLs supporting ……
版权说明:本资料由用户提供并上传,仅用于学习交流;若内容存在侵权,请进行举报,或 联系我们 删除。
PARTNER CONTENT
相关评论 (下载后评价送E币 我要评论)
没有更多评论了
  • 可能感兴趣
  • 关注本资料的网友还下载了
  • 技术白皮书