ISE 12 主要信息：功耗优化Power Optimization ISE Design Suite 12 introduces the first automated, intelligent clock-gating technology for FPGA design. With this capability the tool automatically neutralizes unnecessary logic activity, reducing dynamic power usage up to 30%. A unique set of algorithms automatically identifies and neutralizes unnecessary logic activity, a primary contributor to dynamic power inefficiencies. These algorithms utilize the abundant clock enables (CE) found in the Virtex-6 FPGA. Each CE is ideally suited for power optimization as it connects to the basic cluster of the Virtex-6 FPGA fabric (the Slice) and controls a small number of registers (only eight). Although the use of clock gating to suppress unnecessary switching in FPGAs is not a new concept, intelligent, fine-grain clock gating ……