tcl the good the Bad and the Uglyintel

tcl and the TK toolkit

the Design Warriors guide to fpgas

the hardware Verification language

advanced fpga Design architecture

Design recipes for fpgas Peter wilson

understanding clock domain crossing issues

US Navy vhdl modelling guide

introduction the verilog hardware Descr

verilog coding for logic synthesis

verilog hdl synthesis practical PrimerBhasker

vhdl coding styles methodologies kluwer

vhdl 2008 Just the New stuff

vhdl logic synthesis approach kluwer academic

frequency domain controller Design method

frequency domain step response identifi

General approach to pid optimal Design