原创 为AM335x移植Linux内核主线代码(20)关于差分线

AM335x主控板的调试卡在了PHY芯片上，反复检查原理图和焊接AR8031，以及反复读取并理解AR8031寄存器的值之后，目前认为Ethernet的Auto-negotiation失败的原因可能是布线问题带来的。所以，暂时打算另外绘制PHY实验板，并且着重了解差分线的布线规则。

## ** 谨以此文祭奠我第一块惨不忍睹的高速差分PCB板，哦耶 =_=!!! ** ##

1. 怎样使用Cadsoft Eaglel布差分线？
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Eagle布局弧线的能力简直无与伦比，同时它支持差分线的布局。在它的帮助手册中：
Editor Commands -> ROUTE -> Differential Pair routing
里面描述了差分线的布局步骤。

 * A differential Pair consists of two signals that have the same name, only one ending with _P (the "positive" signal) and the other one with _N (the "negative" signal), for instance CLOCK_P and CLOCK_N. The two signals must also belong to the same net class.
（当net设置为*_P和*_N的时候，Eagle会认为它们是一对差分线，比如PHY芯片的TX_P和TX_N。当然这两个net要属于同一个net class，Eagle默认整块板都属于同一个class，class default。）

 * When selecting an airwire of a Differential Pair, both signals are routed in parallel. The distance between the two signals as well as the wire and via sizes are determined by the signals' net class. This is done independent of the setting of "Options/Set/Misc/Auto set route width and drill".
（当两根线是差分线时，它们的线宽、距离、过孔规格等等都由net class的特征决定，与当前的布线设置没有关系。在Edit -> Net class...里面能够增加新的net class，设置好线宽、间距等等，然后将net的properties相应的修改过来，如图：）  

 
 (当点击Route按钮布局时，这对差分线就会同时出现，如图：)

 
 * If you don't want to route both signals, you can press the ESCape key to drop the second airwire.
（如果不想同时布这两根线，比如在RJ45变压器引脚附近的时候，可以使用ESC键丢掉第二根airwire。）
 
 * At the beginning of routing a Differential Pair (when the starting points of the airwires don't have the necessary distance, yet) signal wires are generated from the starting points to the current mouse cursor position, according to the current wire bend style.  Note that there may be cases where these wires overlap, so please make sure you choose a proper point from where to start the actual paraller routing.
（差分线的起点是鼠标当前的位置，并且基于现在的bend style，这可能会造成线的重叠（这个使用鼠标右键多点击几次，选择比较合适的bend style即可）。）

 * The coordinates given while routing a Differential Pair form a "center line" along with the actual signal wires are placed left and right with the proper distance.
 * Since the pads a Differential Pair is connected to typically don't have the same distance as used for the signal wires, you may have to route such signals from both ends. This means, you start at one part, route towards the other part, and then route the rest starting from the other part. This is necessary because only the first step in a routing sequence generates wires that start at positions that don't have a proper distance.
（器件引脚离差分线的距离通常不一致，所以可以分别从两个器件开始布线，从而产生合适的间距。）
 
 * If you route towards the wire end points of a Differential Pair in a different layer, and the wires are fully aligned, the proper vias will generated automatically.
 （在不同层之间布差分线，vias会自动生成。如图所示：（当然过孔应该尽量避免））

 * The special mouse key functions Shift+Left (place a via at the end point) and Ctrl+Left (define arc radius) don't work in Differential Pair mode.
（Shift+Left以及Ctrl+Left快捷键是差分模式下是不能使用的。）
 
 * Differential Pairs can only be routed fully manually. The Follow-me router and the Autorouter treat them like regular signals.
（差分线只能手动布局。）
 
2. 在高速差分线中，经常听到阻抗这个概念，但一直没有弄清楚它的含义，因此趁调试PHY芯片的机会了解一下它，也学习其它的高速布线规范：
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《High-Speed Layout Guidelines》- Texas Instruments
1. Theoretical Overview
1.1 Electromagnetic Interference and Electromagnetic Compatibility

Electromagnetic interference (EMI) is radio frequency energy that interferes with the operation of an electronic device. This radio frequency energy can be produced by the device itself or by other devices nearby.

（EMI的概念。电磁辐射，主要指对其它设备的影响。）

Electromagnetic compatibility (EMC) is the ability of an electronic product to operate without causing EMI that would interfere with other equipment and without being affected by EMI from other equipment or the enviroment.

（EMC的概念。电磁兼容性，主要指设备自身不产生EMI，以及不受其它设备EMI影响的能力。）

1.2 Clock Signals

（根据傅立叶变换可知，时钟信号由一系列的正弦信号和余弦信号组成，它们的频率幅值由时钟信号的上升下降沿决定。而且，频率越高，辐射越大。）

1.3 Transmission Lines

If the lengths of traces are in the range of the signal's wavelength, the the user has to be consider the effects of transmission lines. The problem that a user must deal with are time delay, reflections, and crosstalk. To get a better understanding of these problems and where and how they arise, it is useful to know what transmission lines are. They are simply the traces on a PCB and depend on the length and the frequency of the signals passing through them.

（如果传输线的长度在信号波长的范围内，就需要考虑传输线效应。）

Many different structures of trace routing are possible on a PCB. Two common structures are shown in Figure 3. On the left, a microstrip structure is illustrated and on the right, a stripline technique. A microstrip has one reference, often a ground plane, and these are seperated by a dielectric. A stripline has two references, ofen multiple ground planes, and are surrounded with the dielectric.

（很重要的微带线和带状线的概念。微带线走在表面，带状线走在内层；。带状线的辐射不会出去。）
 

Figure 3. Structure and Dimension of Microstrip and Stripline
 

Figure 4. Calculation of Properties of Microstrip and Stripline (AppCAD)

1.3.1 Signal Speed and Propagation Delay Time
1.3.1.1 Examples
1.3.2 Characteristic Impedence, Reflections, and Termination

（当特征阻抗发生变化的时候，信号反射就会发生。极端情况比如特征阻抗从无穷大变成0的时候。反射系数描述了传输线阻抗和源阻抗之间的关系：当传输线阻抗为无穷大时，反射系数为1；当传输线阻抗为0时，反射系数为-1。为1意味着信号会完全反射回来。反射系数最好为0，也就是信号源阻抗最好等于传输线特征阻抗。）

（下图是信号源阻抗为25欧姆，特征阻抗为50欧姆，负载阻抗无穷大时的信号波形：）
 

Figure 5. Over- and Undershoots Due to Incorrect Termination       

(红线是理想波形，绿线是时钟输出点的实际波形，蓝线是传输线终点的波形。)

（*之前调试74HC595串联的静驱数码管时，也遇到了时钟信号反射的问题，导致出现乱码。当降低了时钟线上升下降沿的频率，或者在时钟输出点放置50欧姆电阻，时钟波形会变好，乱码会消失。）

1.4 Crosstalk

The mutual influence of two paraller, nearby routed traces is called crosstalk. One is called the aggressor (this trace carries the signal) and the other is called the victim (this trace is influenced by the aggressor). Due to the electromagnetic field, the victim is influenced by an inductive and a capacitive coupling. They generate a forward and a backward current in the victim trace whereas in a homogenous environment cancel each other. In a microstrip environment, the forward current of the inductive coupling tends to be larger than the influence of the capacitive coupling. To minimize the effects on crosstalk on adjacent traces, keep them at least 2 times the trace width apart.  

（差分线的间距要在线宽的2倍以上。）

1.5 Differential Signals
1.6 Return Current and Loop Areas

（高速电路的回流路径和低速电路不同，它是沿信号线的背面返回，因此要确保信号线的背面地平面连续。）

2. Practical PCB Design Rules
2.1 PCB Considerations During the Circuit Design

 * What is the highest frequency and fastest rise time in the system?
 * What are the electrical specifications at the inputs and outputs of the sinks and the sources?
 * Are there sensitive signals to route - for example, think about controlled impedance, termination, propagation delay on a trace (clock distribution, buses, etc.)?
 * Is a microstrip adequate for the sensitive signals, or it essential to use stripline technique?
 * How many different supply voltages exist? Does each supply voltage need its own power plane, or is it possible to split them?
 * Create a diagram with the functional groups of the system -e.g., transmitter path, receiver path, analog signals, digital signals, etc.
 * Are there any interconnections between at least two independent functional groups? Take special care of them. Think about the return current and crosstalk to other traces.
 * Clarify the minimum width, separation and height of a trace with the PCB manufacturer. What's the minimum distance between two layers? What about the minimum drill and the requirements of vias? Is it possible to use blind vias and buried vias?
 
2.2 Board Stackup

（最好使用多层板，而且设置合理的板层用途。）

2.3 Power and Ground Planes

As previously mentioned, a complete ground plane in high-speed design is essential. Additionally, a complete power plane is recommended as well. In a complex system, several regulated voltage can be present. The best solution is for every voltage to have its own layer and its own ground plane. But this would result in a huge number of layers just for ground and supply voltages. What are the alternatives? Split the ground planes and the power planes? In a mixed-signal design, e.g., using data converters, the manufacturer often recommands splitting the analog ground and the digital ground to avoid noise coupling between the digital part and the sensitive analog part.

Take care when using split ground planes because:

 * Split ground planes act as slot antennas and radiate.
 * A routed trace over a gap creates large loop areas, because the return current cannot flow beside the signal, and the signal can include noise int the nonrelated reference plane.
 * With a proper signal routing, crosstalk also can arise in the return current path due to discontinuties in the ground plane. Always take care of the return current.
 * If possible, use a continues ground plane; do not split them. This can be achieved by a proper placement selection. Again, create functions blocks, and place and route them together. By doing this, the traces of a digital part cannot influence any trace of the analog part if these sections do not across each other.
（使用整块地的方案是比较合适的，分隔的地会带来各种各样的问题，这和低速电路的概念是不一样的。）

If split ground planes are essential:
 * Do not route signals over a gap. Always strive for the return current flow with the smallest loop area.
 * Connect split ground planes only at one point. More common ground connections can create ground loops, and this increases radiation.
 * The return current of a subsystem (e.g., an analog system or transmitter path) must not be in the path of the other subsystem (digital system or receiver path). The return current should flow directly to the common ground point.
 * Power planes should only reference their own ground plane. They should not overlap with another grond plane. This leads to capacitive coupling between the power plane and a not-referenced ground plane. Noise can couple into the other system.
 * Do not connect bypass capacitors between a power plane and an unrelated ground plane. Again, noise can be coupled from one supply system into the other. This mistage can occur in the circuit design section.

 （如果使用分隔地的话，需要。。。还是使用整块地吧！）
 
 2.4 Decoupling Capacitors
 
Decoupling capacitors between the power pin and ground pin of the device ensure low ac impedance to reduce noise and to store energy. To reach low impedance over a wide frequency range, several capacitors must be used. This is why, a real capacitor consists of its capacitance and a parasitic inductance and register. Therefore, every real capacitor behaves as a resonant circuit. The capacitive characteristics are only valid up to its self-resonant frequency (SRF). Above the SRF, the parasitic effects dominate, and the capacitor acts as an inductor. With the use of several capacitors with different values, low ac impedance over a wide frequency range can be provided.

（使用不同容值的电容组合来旁路，效果更好。）

Capacitors with high values have low impedance in the lower frequency range and a low SRF, whereas small-valued capacitors have their SRF in the upper frequecy range. This depends on the equivalent series resistance (ESR) and the equivalent series inductance (ESL). A good comination of several capacitors leads to a low impedance over a wide frequency range.

（高容值的电容在低频时有更低的阻抗，小容值的电容的共振频率在高频。）

General rules for placing capacitors:

 * Place the lowest valued capacitor as close as possible to the device to minimize the inductive influence of the trace. This is especially important for small capacitor values, because the inductive influence of the trace is not negligible anymore.
（小容值的电容更应该靠近设备引脚，因为它的电感效应更明显。）
 * Place the lowest valued capacitor as close as possible to the power pin/power trace of the device.
（低容值的电容更靠近设备的电源引脚。）
 * Connect the pad of the capacitor directly with a via to the ground plane. Use two or three vias to get a low-impedance connection to ground. If the distance to the ground pin of the device is short enough, you can connect it directly.
（电容应该通过过孔接地，打两到三个过孔有利于减小阻抗。如果离地线够近，也可以值接连起来。）
 * Make sure that the signal must flow along the capacitor.
（确保信号和电容一起流动。（额，信号怎么和电容一起涅？））

2.5 Trace, Vias, and Other PCB Components

A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner, and the characteristic impedance changes. This impedance change cause reflections.
（布线的直角角度会引发辐射。拐角处电容会增加，特征阻抗会改变，从而引发信号的反射。）

 * Avoid right-angle bends in a trace and try to route them at least with two 45° corners. To minimize any impedance change, the best routing would be a round bend.
（走弧线，而不是直角。）
 * Separate high-speed signal (e.g., clock signals) from low-speed signals and digital from analog signals; again, placement is important.
（高速线与其它线分开。）
 * To minimize crosstalk not only between two signals on one layer but also between adjacent layers, route them with 90° to each other.
 （不同的差分线呈90°走在不同层。）

        Figure 13. Poor and Good Right Angle Bends
 
The use of vias is essential in most routings. But the the designer has to be careful when using them. They add additional inductance and capacitance, and reflections occure due to the change in the characteristic impedance. Vias also increase the trace length.
 （尽量避免过孔。）
 * Avoid vias in differential traces. If it is impossible to avoid them, use vias in both traces or compensate the delay also in the other trace.
（过孔的位置会影响回流路径。）
（盲埋孔比通孔要好，是因为通孔造成了一个高阻抗的负载端。）

Tips for routing traces and the use of vias:

 * Do not use right-angle bends on traces with controlled impedance and fast rise time, respectively.
 * Route the traces orthogonally to each other on adjacent layers to avoid coupling.
 * To minimize crosstalk, the distance between two traces should be approximately 2 to 3 times the width of the trace.
 * Differential traces should be routed as close as possible to get a high coupling factor. As a result of this, influenced noise is then a common-mode noise and is not a problem for a differential input stage.
 * Do not use vias on traces with sensitive signal, if unnecessary.
 *Be careful with the return current when changing the layers. Use ground vias around the signal via to make sure that the return current can flow as close as possible to the signal.
 * Do not create slots, for example in the ground plane, by using closely placed vias.
 * Consider stubs created by vias. If necessary, use blind vias or buried vias.
 
2.6 Clock Distribution
Summary

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准备完知识之后，就可以下手更改俺的PCB板了！
泪奔中～