采用DSP builder v9.1实现正交两路单频输出，已经在EP3C80上面跑通，经实际验证是正确的。此例程非常简洁明了，可以作为DSP builder的入门示例。里面已经包含了生成好的modelsim仿真示例和仿真结果。EP3C80\CIC_CONST_DECIM.v......\db\altsyncram_2op3.tdf......\..\altsyncram_9ou3.tdf......\..\altsyncram_a2n3.tdf......\..\altsyncram_dkp3.tdf......\..\altsyncram_dl31.tdf......\..\altsyncram_fi31.tdf......\..\altsyncram_gum3.tdf......\..\altsyncram_h2s3.tdf......\..\altsyncram_kku3.tdf......\..\altsyncram_lv14.tdf......\..\altsyncram_nur3.tdf......\..\alt_dspbuilder_AROUND.vhd......\..\alt_dspbuilder_ASAT.vhd......\..\alt_dspbuilder_cast.jvgen_cache.xml......\..\alt_dspbuilder_cast.vhd......\..\alt_dspbuilder_cast_GN4KSUFGA2.vhd......\..\alt_dspbuilder_cast_GNLHWQIRQK.vhd......\..\alt_dspbuilder_cast_GNYS2BYR3H.vhd......\..\alt_dspbuilder_clock.jvgen_cache.xml......\..\alt_dspbuilder_clock.vhd......\..\alt_dspbuilder_clock_GNF343OQUJ.vhd......\..\alt_dspbuilder_gnd.jvgen_cache.xml......\..\alt_dspbuilder_gnd.vhd......\..\alt_dspbuilder_gnd_GN.vhd......\..\alt_dspbuilder_IncDecAltr.vhd......\..\alt_dspbuilder_inc_dec.jvgen_cache.xml......\..\alt_dspbuilder_inc_dec.vhd......\..\alt_dspbuilder_inc_dec_GNWMA7DC6Y.vhd......\..\alt_dspbuilder_logical_bit_op.jvgen_cache.xml......\..\alt_dspbuilder_logical_bit_op.vhd......\..\alt_dspbuilder_logical_bit_op_GN3XV4RTPK.vhd......\..\alt_dspbuilder_lut.jvgen_cache.xml......\..\alt_dspbuilder_lut.vhd......\..\alt_dspbuilder_lut_GNSFEBRPUK.hex......\..\alt_dspbuilder_lut_GNSFEBRPUK.vhd......\..\alt_dspbuilder_lut_GNWKDMB5P3.hex......\..\alt_dspbuilder_lut_GNWKDMB5P3.vhd......\..\alt_dspbuilder_port.jvgen_cache.xml......\..\alt_dspbuilder_port.vhd......\..\alt_dspbuilder_port_GNBO6OMO5Y.vhd......\..\alt_dspbuilder_port_GNS2GDLO5E.vhd......\..\alt_dspbuilder_port_GNXAOKDYKC.vhd......\..\alt_dspbuilder_rom.jvgen_cache.xml......\..\alt_dspbuilder_rom.vhd......\..\alt_dspbuilder_rom_GN5WIXXSQD.hex......\..\alt_dspbuilder_rom_GN5WIXXSQD.vhd......\..\alt_dspbuilder_rom_GNLUZ4Y63B.hex......\..\alt_dspbuilder_rom_GNLUZ4Y63B.vhd......\..\alt_dspbuilder_sAltrBitPropagate.vhd......\..\alt_dspbuilder_sAltrPropagate.vhd......\..\alt_dspbuilder_SBF.vhd......\..\alt_dspbuilder_SBitLogical.vhd......\..\alt_dspbuilder_testbench_capture.jvgen_cache.xml......\..\alt_dspbuilder_testbench_capture.vhd......\..\alt_dspbuilder_testbench_capture_GN32ABLG7V.vhd......\..\alt_dspbuilder_testbench_capture_GNAXODEVVW.vhd......\..\alt_dspbuilder_testbench_capture_GNZUHKKGTG.vhd......\..\alt_dspbuilder_testbench_clock.jvgen_cache.xml......\..\alt_dspbuilder_testbench_clock.vhd......\..\alt_dspbuilder_testbench_clock_GNCGUFKHRR.vhd......\..\alt_dspbuilder_testbench_salt.jvgen_cache.xml......\..\alt_dspbuilder_testbench_salt.vhd......\..\alt_dspbuilder_testbench_salt_GNVU5PG7ZL.vhd......\..\alt_dspbuilder_vcc.jvgen_cache.xml......\..\alt_dspbuilder_vcc.vhd......\..\alt_dspbuilder_vcc_GN.vhd......\..\alt_dspbuilder_vecseq.vhd......\..\alt_synch_pipe_ikd.tdf......\..\alt_synch_pipe_jkd.tdf......\..\alt_synch_pipe_sld.tdf......\..\alt_synch_pipe_tld.tdf......\..\a_gray2bin_lfb.tdf......\..\a_gray2bin_vgb.tdf......\..\a_graycounter_fic.tdf......\..\a_graycounter_gic.tdf......\..\a_graycounter_k47.tdf......\..\a_graycounter_pjc.tdf......\..\a_graycounter_qjc.tdf......\..\a_graycounter_u57.tdf......\..\cmpr_656.tdf......\..\cmpr_efc.tdf......\..\cmpr_g66.tdf......\..\cmpr_ifc.tdf......\..\cmpr_jfc.tdf......\..\cntr_3fi.tdf......\..\cntr_6fi.tdf......\..\cntr_p1j.tdf......\..\cntr_v7j.tdf......\..\dcfifo_6rl1.tdf......\..\dcfifo_lvl1.tdf......\..\decode_4uf.tdf......\..\dffpipe_8d9.tdf......\..\dffpipe_gd9.tdf......\..\dffpipe_hd9.tdf......\..\dffpipe_id9.tdf......\..\dffpipe_qe9.tdf......\..\dffpipe_re9.tdf......\..\dffpipe_se9.tdf......\..\DSPBuilderSin.asm.qmsg……