32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories and
between registers)
32-bit multiplier (fastest instruction execution takes one CPU clock cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
JTAG and FINE (two-line) debugging interfacesFeatures
RX63N Group, RX631 Group
Renesas MCUs R01DS0098EJ0100
Rev.1.00
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash Jun 13, 2012
memory, Ethernet MAC, full-speed USB 2.0 host/function/OTG interface,
various communications interfaces including CAN, 10- & 12-bit A/D
converters, RTC
Features
RX63N Group products incorporate an Ethernet controller while PLQP0176KB-A ……
