TAU/BLAST Support in 2.1i APPLICATION NOTE TAU/BLAST Support in 2.1i XAPP166 August 9, 1999 (Version 1.0) Application Note Summary The Xilinx 2.1I development system adds Stamp Model Generation. This feature supports the use of board level Static Timing Analysis tools, such as Mentor Graphics' Tau and Viewlogic's Blast. With these tools, users of Xilinx programmable logic products can accelerate board level design verification. TAU/BLAST Support in 2.1i For FPGA families, the Xilinx 2.1i program trce has the ability to produce STAMP files that will be used to pass the timing data about the Xilinx FPGA to Tau/Blast. By default tr……