This application note describes the flow for implementing fractional phase-locked loop (PLL) reconfiguration and dynamic phase shifting for fractional PLLs in 28-nm devices (Arria® V, Cyclone® V, and Stratix® V device families) with the ALTERA_PLL and ALTERA_PLL_RECONFIG megafunctions in the Quartus® II software. Implementing Fractional PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions AN-661-1.0 Application Note This application note describes the flow for implementing fractional phase-locked loop (PLL) reconfiguration and dynamic phase shifting for fractional PLLs in 28-nm devices (Arria V, Cyclone V, and Stratix V device families) with th……