原创 Can I use a Programmable Clock Output (PCKx pin) t

 2010-7-6 16:10  3167 4 4 分类: MCU/ 嵌入式

PLLCK为时钟源，分频系数为1

PLLCK的MUL=25,DIV=5，即PLLCK为96MHz左右

20M以上波形已经变成三角波而且幅值变小很多

Question
Can I use a Programmable Clock Output (PCKx pin) to clock my Ethernet PHY?
Answer
Most of our on-chip PLLs feature 5% max of cycle jitter in percent of the output clock period. Ethernet PHY are used to having a frequency tolerance of ±50ppm. That means it is not possible to generate a frequency with a tolerance of ±50ppm through our PLL and so on a PCKx output pin. A PCKx pin can not be used to clock an external PHY.

Question

Can I use a Programmable Clock Output (PCKx pin) to clock my Ethernet PHY?

Answer

Most of our on-chip PLLs feature 5% max of cycle jitter in percent of the output clock period.

Ethernet PHY are used to having a frequency tolerance of ±50ppm.

That means it is not possible to generate a frequency with a tolerance of ±50ppm through our PLL and so on a PCKx output pin.
A PCKx pin can not be used to clock an external PHY.

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