原创 三分频50%占空比电路的VHDL可综合代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------------------
entity div3 is
port(
    clk_in    :    in    std_logic;
    clk_out    :    out std_logic
    );
end div3;
------------------------------------------
architecture behav of div3 is
signal count1 : std_logic_vector(1 downto 0);
signal count2 : std_logic_vector(1 downto 0);
signal q      : std_logic;
signal outclk1: std_logic;
signal outclk2: std_logic;
begin
    q         <= outclk1 and outclk2;
    clk_out    <= q xor outclk1;
    -------------------------------
    process(clk_in)
    begin
        if clk_in'event and clk_in = '1' then
            if count1 = "00" then
                outclk1 <= '0';
                count1  <= count1 + 1;
            elsif count1 = "01" then
                outclk1 <= '1';
                count1  <= count1 + 1;
            elsif count1 = "10" then
                outclk1 <= '1';
                count1  <= "00";
            end if;
        end if;
    end process;
    -------------------------------
    process(clk_in)
    begin
        if clk_in'event and clk_in = '0' then
            if count2 = "00" then
                outclk2 <= '1';
                count2  <= count2 + 1;
            elsif count2 = "01" then
                outclk2 <= '0';
                count2  <= count2 + 1;
            elsif count2 = "10" then
                outclk2 <= '0';
                count2  <= "00";
            end if;
        end if;
    end process;
    ---------------------------------
end behav;