原创 Altera Forum精彩问答汇总

坛中一日，人间数年！

I can't afford losing any of this kind of invaluable information anymore! It is not too late if I start reading and collecting them from now on. I will look the threads through everyday as I do with my Hotmail E-mails and EETimes RSSs.

It's all about Timing：

Sun Nov 08 2009 09:35:01 GMT+0800 Timing Analysis of a Source Synchronous Interface Using ALTLVDS Thanks again! Kwalt.

Wed Nov 4 2009 21:01:49 UTC+0800 Slack:Not operational: Clock Skew>Data Delay ... No answers yet. Do an experiment myself.

Wed Nov 4 2009 20:46:41 UTC+0800 Timing constraints for ALTLVDS I/O 

Wed Nov 4 2009 20:44:29 UTC+0800 Constraining SOPC Builder designs using TimeQuest
Wed Nov 04 2009 00:26:23 GMT-0800 (Pacific Standard Time) Instantiate primitive DFF with an an inverted clock input "the inverter get absorbed into the LAB clock inversion and there is no clock skew and no timing issues"
Wed Nov 04 2009 00:12:59 GMT-0800 (Pacific Standard Time) Timing Analysis of Internally Generated Clocks in Timequest   kwalt, How many thanks I owe you!
Wed Nov 04 2009 00:11:35 GMT-0800 (Pacific Standard Time) The inconsistent results of the Timequest
Wed Nov 04 2009 00:08:23 GMT-0800 (Pacific Standard Time) How to Constraint Source-Synchronous Double-Data Rate Interfaces
Wed Nov 04 2009 00:07:33 GMT-0800 (Pacific Standard Time) Recovery timing errors using clock crossing bridge
Wed Nov 04 2009 00:04:29 GMT-0800 (Pacific Standard Time) set_clock_groups notes
Wed Nov 04 2009 00:02:47 GMT-0800 (Pacific Standard Time) case analysis and false path issues
Wed Nov 04 2009 00:00:51 GMT-0800 (Pacific Standard Time) Timequest: WHY? Pros and Cons!
Tue Nov 03 2009 23:40:59 GMT-0800 (Pacific Standard Time) Centering the Clock in the Data Valid Window for Source Syncrhonous Inputs
Tue Nov 03 2009 23:39:04 GMT-0800 (Pacific Standard Time) Timing Analysis of Source Synchronous Outputs
Tue Nov 03 2009 23:38:08 GMT-0800 (Pacific Standard Time) Implementing a Source Synchronous Interface between Altera FPGAs v2.0
Tue Nov 03 2009 23:24:57 GMT-0800 (Pacific Standard Time) Clock setup and hold slack explained
Tue Nov 03 2009 23:11:44 GMT-0800 (Pacific Standard Time) Applying multicycle assignments
Sun Nov 01 2009 17:17:32 GMT+0800 signal transfer in different clock domains
Sun Nov 01 2009 16:53:26 GMT+0800 Implementation and Timing of Reset Circuits
Sun Nov 01 2009 16:46:41 GMT+0800 Timequest & Output delay problem "I've found it easy to totally get wrapped up into equations and lost in the details."
Sun Nov 01 2009 16:39:19 GMT+0800 PLL Compensation warning Still not quite clear about this. Need to do a experiment myself.
Sun Nov 01 2009 16:37:35 GMT+0800 I need a low jitter clock mux in logic cells "We then use a phase-frequency detector to track the difference between the CRU clock and the reference clock. We can then tune our reference clock to match the frequency of the CRU clock." Have I missed out similar in-house designs?
Sun Nov 01 2009 16:36:16 GMT+0800 Understanding Recovery and Removal in TimeQuest Will study it carefully when I have time.
Sun Nov 01 2009 16:35:14 GMT+0800 Ripple and gated clocks: clock dividers, clock muxes, and other logic-driven clocks This one really helps. It guided my recent work to a success!

On the Boundaries:

Wed Nov 04 2009 21:32:58 GMT+0800 are all GND pins connected internally to GND?

Wed Nov 4 2009 20:51:20 UTC+0800 SMII to MII converter ref design

Wed Nov 4 2009 20:48:46 UTC+0800 Stratix II DPA Reference design
Tue Nov 03 2009 23:47:52 GMT-0800 (Pacific Standard Time) CDR Data Non-Randomness Detection
Tue Nov 03 2009 23:32:33 GMT-0800 (Pacific Standard Time) Migrating Xilinx V2-Pro MGTs to Altera Stratix II GXBs
Sun Nov 01 2009 17:08:20 GMT+0800 how to sample io pin using signaltap 2 logic analyzer? Need to do some experiments myself.
Sun Nov 01 2009 17:06:40 GMT+0800 lvds simulation of stratix 4 using cst design studio Can anyone help him/her/me?
Sun Nov 01 2009 17:04:11 GMT+0800 What kind of pad does the Quartus select when I configure the i/o as single-ended
Sun Nov 01 2009 17:01:12 GMT+0800 Differential pair and Single-ended pins in HSMC of StratixIII 3SL150 kit
Sun Nov 01 2009 16:55:36 GMT+0800 how to connect PLL output to default pin What we can do or what we cannot do with the PLLs/Clkctrls are never clear until we reached the P&R stage. Isn't this inconvenient?

Call me a "Flow Guy":
Sun Nov 01 2009 17:15:04 GMT+0800 How to maximize license utilization? Help myself!
Sun Nov 01 2009 17:03:16 GMT+0800 log files generated by Quartus. Can anyone help him/her/me?
Sun Nov 01 2009 16:50:47 GMT+0800 Handling Quartus executable return codes I've long been planning on a blog post about how to control the compilation flow within Tcl.

Tricks:
Sun Nov 01 2009 17:21:42 GMT+0800 How to extract 1bit from a bus in a Block Diagram/Schematic File
Sun Nov 01 2009 17:12:13 GMT+0800 X_on_violation_option

IPs:

Wed Nov 4 2009 21:06:29 UTC+0800 programmable input output slave peripheral with programmable interrupts
Tue Nov 03 2009 23:42:14 GMT-0800 (Pacific Standard Time) Example of a PLL lock circuit using logic Interesting!
Tue Nov 03 2009 23:22:47 GMT-0800 (Pacific Standard Time) Synthesizing Equations What a gentleman!
Tue Nov 03 2009 23:04:02 GMT-0800 (Pacific Standard Time) Hardware version number
Tue Nov 03 2009 23:00:56 GMT-0800 (Pacific Standard Time) Avalon MM Master VHDL Templates
Tue Nov 03 2009 22:59:26 GMT-0800 (Pacific Standard Time) Avalon OpenCores 10/100 Ethernet MAC with InterNiche driver

Configuration:

Wed Nov 4 2009 20:58:50 UTC+0800 jtag player: eCos=>CyclII & epcs
Tue Nov 03 2009 23:45:48 GMT-0800 (Pacific Standard Time) Configuration estimator on Cyclone III
Tue Nov 03 2009 23:44:06 GMT-0800 (Pacific Standard Time) Programming EPCS devices with JTAG
Tue Nov 03 2009 23:33:19 GMT-0800 (Pacific Standard Time) Design example for Remote System upgrade
Tue Nov 03 2009 23:12:41 GMT-0800 (Pacific Standard Time) Fast Passive Parallel Configuration Controller Design

Simulation:

Wed Nov 4 2009 20:55:58 UTC+0800 Using hardware to accelerate simulation - ref design

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