原创 22nm & below: Low power against high performance

Intel's decision to shift to new 22nm CMOS process technology in its Atom CPU road map has disturbed a delicate balance preserved over the last ten years or so among circuit designers, processor architects, and embedded system hardware and software developers.

What is upsetting the balance and may force a rethink of every aspect of embedded systems design is Intel's shift away from a well understood planar structure to a vertical 3D FinFET. The company claims that going vertical allows significantly higher performance at lower power than most planar techniques. If Intel is successful, it will be hard for ARM and its licensees and other CPU architectures to avoid making the jump as well.

In the past, as semiconductor manufacturers went to smaller nanometer geometries with traditional planar CMOS designs, developers at all levels—circuit and logic design, processor architecture, and software development—have been able to adjust.

Working within the planar CMOS structure, they found ways to not only take advantage of the improvements in density, performance and power, but also deal with the problems of leakage, noise, reliability, EMI and ESD that nanometer scaling caused.

Several questions occur to me. If such a change is necessary, are the tough issues relating to reliability and performance with vertical FinFET structures well understood? And will many of the techniques developers have developed in planar CMOS designs still apply? Or will everything have to be rethought? Is such a vertical move at the process level necessary across all embedded CPU designs? Or is it something forced on Intel by the nature of its X86 architecture?

I would like to hear from you, pro and con, in the form of blogs and opinion commentary and as design articles about how you are dealing with the changes.