面向 Virtex-4 FPGA 的可综合 CIO DDR RLDRAM II 控制器 Application Note: Virtex-4 Family R Synthesizable CIO DDR RLDRAM II Controller for Virtex-4 FPGAs XAPP710 (v1.3) April 19, 2007 Author: Benoit Payette Summary This application note describes how to use a Virtex-4 device to interface to Common I/O (CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices. The reference design targets two CIO DDR RLDRAM II devices at a clock rate o……