用户1523359的文章-第2页-面包板社区

 

文章

首页 我的博文

用户1523359 2010-11-2 17:47: contemplation; submodle at least should do behaviour simulation.; 981 13 0 13

用户1523359 2010-11-2 17:43: modelsim simulation detail; Clock Generator: use always begin # (CLK_PERIOD/2) SYS_CLK = ~SYS_CLK; end always begin # (DMTCLK_PERIOD/2) DVI_CLK = ...; 1092 9 0 9

用户1523359 2010-11-2 13:21: Xilinx Timing Q & A; Q1: Does the tool analyze the path crossing clock domain when timing analysis? Can I see the results in the timing reports? A1: It analyzes the cro ...; 1446 17 0 17

timing

用户1523359 2010-11-2 13:15: xilinx setup and hold time; from http://forums.xilinx.com/t5/Timing-Analysis/Hold-time-can-be-negative-zero-and-positive-can-you-explain-it/m-p/101052 ============= The easy w ...; 1797 16 1 17

timing

用户1523359 2010-11-1 18:24: Xilinx PlanAHead 11.5 introduction; PlanAHead 11.5 replace s the current PACETM I/O pin planning tool and the previous ISE floorplanning tools. ========== Some terms: 1. When Projec ...; 1708 8 0 8

用户1523359 2010-10-28 15:38: Xilinx Constraints Terminology; I myself have been trapped by these similar terminology for a while. Here's for others' reference and my contemplation. general: Primitive and macr ...; 1352 10 0 10

xilinx constraint

用户1523359 2010-10-27 16:56: modelsim (6.5c) compile; compile methods: 1. bat (1) cmdcompxlib -s mti_se -dir all -l all -o c:\Modeltech _6.5d\xilinx_libs -p c:\Modeltech_6.5d\win32 where c:\Modeltech ...; 2076 12 1 13

modelsim compile

用户1523359 2010-10-27 16:49: mdelsim (6.5c) installation; installation: 1. install modelsim (6.5c) (1) "No" when installing Security Key (2) "Exit" when configuring Liscense Wizard 2. crack modelsim (6.5c ...; 1491 9 0 9

modelsim

12 / 2 页

关闭站长推荐

上一条

/3

下一条