introduction the verilog hardware Descr

Verification Methodology manual for systemverilog

understanding clock domain crossing issues

uml for SoC Design

tutorial FloatingPoint arithmetic on fpgas

logic synthesis for fpga reliability

logic Design for reliability

Design recipes for fpgas Peter wilson

advanced fpga Design architecture

towards and xor balanced synthesis

timing Verification of asics

the verilog golden reference guide

the verilog hardware description language 5th

the fundamentals of efficient synthesizable

the hardware Verification language

test considerations for PLDsti

technical implementation of the HighSpee