dft ATPG and BISTslidesHsinPo Wang

Fourteen Ways to Fool your synchronizer

art of writing test Benches

power considerations in fpga DESIGNlattice

writing efficient Testbenchesxilinx

synchronous resets asynchronous resets

the verilog golden reference guide

fpga high efficiency Low noise pulse frequenc

designing Safe verilog State machines With

dft compiler Next Generation1Pass te

基于 fpga 设计 功能仿真 时序仿真

creating Safe State machines

fpga 设计方法 技巧 资料 fsm 设计 指导

Xilinx Design reuse Methodology for ASIC

asynchronous fifo architectures

大型 设计 fpga 多时钟 设计策略

关于 maoci 讨论 可靠性 几个 概念