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用户193865 2009-5-11 09:59: DFT Compiler的学习-----part3 Pre-scan的test DRC; 关于pre-scan的test DRC问题 1.test DRC的流程很简单，只要注意到只有在创建test_protocol之后才可能test DRC检查。 2.test DRC后时序单元的分类分为两类， ...; 6287 9 0 7

用户193865 2009-5-11 09:57: DFT Compiler的学习-----part6 Report和Output File; 1.preview_dft 功能：在做inser_dft之前查测试点的信息，扫描链的信息。根据这些信息来确定所加的dft 规格是否完备。一般是在规则写完并进行dft_drc之后，用 ...; 5279 7 1 7

用户193865 2009-5-11 09:57: DFT Compiler的学习-----part2 scan replacement; 今天着重分析下扫描单元替换（scan replacement）的内容。所谓scan replacement，顾名思意就是在设计中用扫描单元替代非扫描单元。如果设计是以RTL形式给出的， ...; 4351 9 0 5

用户193865 2009-5-8 18:04: PERL unicode; 本文内容适用于perl 5.8及其以上版本. perl internal form 在Perl看来, 字符串只有两种形式. 一种是octets, 即8位序列, 也就是我们通常说的字节数组. 另一 ...; 2329 7 0 6

用户193865 2009-4-26 14:49: verification question; (*) Whats the difference between structural and functional vectors. http://www.eetasia.com/ARTICLES/2004DEC/B/2004DEC01_ICT_ST_TA.pdf ...; 2998 7 0 7

用户193865 2009-4-25 16:22: ASIC Test Methodology Simulation Engineer; Company: Qualcomm Position: ASIC Test Methodology/Simulation Engineer Questions 1. What will happen when there is hold time violation in one o ...; 2322 8 0 8

用户193865 2009-4-25 15:27: PCB布线设计经验谈-模拟和数字布线的异同; 　　工程领域中的数字设计人员和数字电路板设计专家在不断增加，这反映了行业的发展趋势。尽管对数字设计的重视带来了电子产品的重大发展，但仍然存在，而且 ...; 3475 8 0 7

用户193865 2009-4-25 14:50: SYNOPSYS Design Compiler Usage Guidelines; SYNOPSYS Design Compile r Usage Guidelines 1. Design Objects(term definition) - ...; 3521 9 1 10

用户193865 2009-3-31 22:36: interview scenario; bgs : whats diff bet set_max_capacitance and set_load? i dont know ans me: set_max_capacitance applies on pin not on pin and net but set_l ...; 3108 4 0 4

用户193865 2009-3-31 22:09: VLSI Interview question 2; Below interview questions are contributed by ASIC_diehard (Thanks a lot !). Below questions are asked for senior position in Physical Design domain. ...; 8599 7 0 7

用户193865 2009-3-31 22:06: VLSI Interview question; What are the various design changes you do to meet design power targets? Ans: Design with Multi-VDD designs, Areas which requires high perfo ...; 3322 7 0 7

用户193865 2009-3-31 22:00: VLSI Frequently asked interview; VLSI Frequently asked interview Questions with answers To recieve answers freely , just register the mailing list at the right what is the dif ...; 2461 6 0 6

用户193865 2009-3-29 22:51: ASIC Design Flow; ASIC Design Flow Step 1: Prepare an Requirement Specification Step 2: Create an Micro-Architecture Documen ...; 3826 5 0 5

用户193865 2009-3-29 19:22: 一个不错的综合脚本小程序; foreach_in_collection clk { set clk_net ] set clk_pin set flag false if { 0} { echo PIN set_ideal_network ...; 2629 6 0 6

用户193865 2009-3-29 19:20: DC 概论六之multicycle_path; 在讲多周期路径之前，先看下单频率路径的建立关系和保持关系『Design Compiler calculates the default setup and hold relations and derives single-cycle ...; 6041 7 0 7

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