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电容,接线对于DDR3内存的测量
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类别: 制造与封装
时间:2020-01-06
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原标题:Capacitor, Wireing Measures Target Noise of DDR3 Memory 主要内容: 在面前内存高速,大容量的提升下,村田制作所在本文中介绍了一种针对噪声的测量方法,还提供了一种减少接线面积测量MCU评估板上的DDR3的实例。 Capacitor, Wiring Measures Target Noise of DDR3 Memory R ecently, DRAM’s performance is being sped up and its tech- nology has been shifting from DDR2 (double data rate 2) to high-frequency and large-capacity DDR3. As a result, the power supply line of DDR encounters high-frequency power supply noise. The noise of the power supply also causes a problem of jitter and signals are negatively affected. On the other hand, the signal of DDR is differentially trans- ferred, so the number of wiring between the memory controller and the memory IC is increasing. In relation, the rule of equal length wiring makes board design difficult. This article from Murata Manufactur- ing ……
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