FPGA和CPLD-可编程逻辑器件-第348页-面包板社区

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FPGA/CPLD

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ash_riple_768180695 2010-6-23 16:01: [译完] Rapid System Prototyping with FPGAs - 4.6; 4.6 Support Obtaining advanced technical answers or technical clarification from a manufacturer can be challenging. Manufacturers wil ...; 2845 5 0 5

ash_riple_768180695 2010-6-23 16:00: [译完] Rapid System Prototyping with FPGAs - 4.5; 4.5 Training Work to put together the best design team possible. Having the “right” team will have a significant impact on an FPGA ...; 2908 7 0 7

ash_riple_768180695 2010-6-23 15:59: [译完] Rapid System Prototyping with FPGAs - 4.4.3; 4.4.3 Budgets and Scheduling Budgets and schedules are key tools for effective project management. In developing a budget it ...; 3691 4 0 4

ash_riple_768180695 2010-6-23 15:59: [译完] Rapid System Prototyping with FPGAs - 4.4.2; 4.4.2 Design Reviews Design reviews are very important to the FPGA design process. Reviews should be multidisciplinary and include ...; 3636 3 0 3

ash_riple_768180695 2010-6-23 15:58: [译完] Rapid System Prototyping with FPGAs - 4.4.1; 4.4.1 Team Communication Consider having regular informal coordination meetings. They do not have to be long, but they must be ef ...; 2645 6 0 6

ash_riple_768180695 2010-6-23 15:57: [译完] Rapid System Prototyping with FPGAs - 4.4; 4.4 Project Engineering and Management Project management is an important part of an FPGA design effort. Design team members will en ...; 3230 5 0 5

ash_riple_768180695 2010-6-23 15:54: [译完] Rapid System Prototyping with FPGAs - 4.3; 4.3 Defined FPGA Design Process Most organizations have not developed an official defined FPGA design process or procedure. Instead, ...; 3937 4 0 4

ash_riple_768180695 2010-6-23 15:54: [译完] Rapid System Prototyping with FPGAs - 4.2; 4.2 Common Design Challenges and Mistakes An FPGA design mistake may be defined as a design that does not achieve the desired ratio of FPGA resource ...; 3432 5 3 8

ash_riple_768180695 2010-6-23 15:53: [译完] Rapid System Prototyping with FPGAs - 4.1; Chapter 4 System Engineering 4.1 Overview Although the system engineering subject matter in this chapter may be applied towards a conventi ...; 5384 8 3 11

ash_riple_768180695 2010-6-23 15:52: 《基于FPGA的快速系统原型开发》评阅人意见; 国庆放假前，riple曾经跟一家出版社联系过翻译出版《基于FPGA的快速系统原型开发》一书的事，经过了一个多月的等待，得到了否定的答复。原因是该 ...; 3675 9 13 22

用户837343 2010-6-23 15:46: 高级篇：第1章可编程逻辑设计指导原则; 第1章可编程逻辑设计指导原则（1）面积和速度的平衡与互换原则。 “面积”指一个设计所消耗FPGA/CPLD的逻辑资源数量：对于F ...; 3829 6 0 6

用户837343 2010-6-23 14:13: 请教RTL阅读器的使用; 在Quartus II下如何使用RTL阅读器？其作用是什么？ RTL阅读器：在设计和调试的优化过程中，可以使用RTL阅读器观察设计电路的综合结果，同时还可以观察原设计 ...; 3621 6 0 6

ash_riple_768180695 2010-6-23 10:28: 维护遗留代码（8）——当riple遇到ripple（行波时钟）; 在补充完整了时序例外约束，排除了虚假时序违规报告之后，设计中的绝大部分时钟都得到了收敛。但是，仍然有部分关键时钟不能收敛，时序余量总的 ...; 6831 11 3 14

用户244280 2010-6-22 22:13: 毛主席词一首; 我很喜欢毛主席的一些诗词，经常去诵读，下面是毛主席的一首词，是红军长征过程中，攻占了娄山关后毛主席写的，词如下：忆秦娥-娄山关 ...; 2826 11 0 11

用户244280 2010-6-22 22:04: 与君分享---我的一首词; 南国冬暖阳花红枝未枯枝未枯好景处处无心留顾十年漫漫寒窗苦满心抱负却无路却无路愁绪千千泪如雨注 ...; 1865 12 0 12

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