我看夏 宇闻老师的书第97页有个例子，我打算做一下，可是不成功

代码：
  1. `timescale 1 ns/ 1 ps
  2. module LAMP_vlg_tst();
  3. // constants
  4. // general purpose registers
  5. reg eachvec;
  6. // test vector input registers
  7. reg clk;
  8. reg rst_n;
  9. // wires
  10. wire led;
  12. // assign statements (if any)
  13. LAMP i1 (
  14. // port map - connection between master ports and signals/registers
  15. .clk(clk),
  16. .led(led),
  17. .rst_n(rst_n)
  18. );
  20. module M;
  21. initial
  22. $display("Displaying in %m");
  23. endmodule
  25. module top;
  26. M m1();
  27. M m2();
  28. M m3();
  29. endmodule
  31. initial
  32. $dumpfile("myfile.dmp");
  33. initial
  34. $dumpvars;
  35. initial
  36. $dumpvars(1,top); //?
  37. initial
  38. $dumpvars(2,top.m1);
  39. initial
  40. $dumpvars(0,top.m1);
  41. initial begin
  42. $dumpon;
  43. #100000 $dumpoff;
  44. end
  45. initial
  46. $dumpall;
  48. endmodule
提示出错
4.jpg
其实就是两句话有问题
$dumpvars(1,top);
还有一句
$dumpall;
请个高手赐教，谢谢！